08-22-2019 05:23 AM
08-28-2019 04:32 AM
No, not at this time.
When you click on create wrapper it checks what language the project is set to and creates the wrapper based on that.
At this time there are only VHDL or Verilog as options.
08-28-2019 09:07 PM
Hi @yotam ,
There are various features of system verilog which are in roadmap but not sure which one are they. But as per latest Vivado 2019.1 user guide(UG1118) it is recommended to use a Verilog wrapper around a System Verilog file:
Page no. 11 :
And we recommend to follow the user guide.