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Explorer
Explorer
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Registered: ‎05-22-2008

block diagram wrapper generation

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When I generate a wrapper for my block diagram design, the wrapper is in verilog, despite the target language being set to vhdl. It looked like the "generate_target" command is what get's run when one right clocks in vivado to "Create HDL Wrapper.."

All the cores and everything lower in the hierarchy is generated in VHDL, but the wrapper in in Verilog. What gives.

 

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Explorer
Explorer
1,170 Views
Registered: ‎05-22-2008

I figured it out. I think there was an existing .verilog file from the first time I generated it, before changing the target language to vhdl. To get vivado to generate the VHDL file, I deleted the verilog file FROM DISK, amd thereafter the wrapper was generated in vhdl. 

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Highlighted
Explorer
Explorer
1,171 Views
Registered: ‎05-22-2008

I figured it out. I think there was an existing .verilog file from the first time I generated it, before changing the target language to vhdl. To get vivado to generate the VHDL file, I deleted the verilog file FROM DISK, amd thereafter the wrapper was generated in vhdl. 

View solution in original post

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