04-03-2020 05:56 AM - edited 04-09-2020 01:07 AM
I rely on non-project mode. I developed a block design which consists of several IPs. Each IP has its own XDC file. Also I have a XDC file for the entire BD which I load with read_xdc and ends up in constrs_1.
I execute following tcl commands on the block design:
validate_bd_design set_property synth_checkpoint_mode None [get_files *.bd] generate_target all [get_files *.bd] synth_design -rtl -top [current_bd_design]
Q1: Do I correctly understand that asynchronous clock groups will cause AXI Interconnect to implement clock domain crossings automatically when calling "generate_target"?
Q2: My BD is contained within a wrapper (some peripheral logic, I/O mapping, I/O constraints, etc) In this design I load the block design as follows: read_bd bd.bd. However, bd.xdc seems to be ignored. If I elaborate design at this stage and run write_xdc, I get all IP constraints as expected, but no trace of bd.xdc. How come?
04-15-2020 11:08 AM
Q1. Yes, since you used generate_target all - it should include the implementation target - which should generate the necessary data for implementing the IP.
Q2. I may be able to dive deeper into the issue if I can reproduce the issue. Would you be able to share these IPs so I can debug it?
You can send the files over Xilinx's secure file transfer: Xilinx EZMove File Transfer Service