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3,437 Views
Registered: ‎01-02-2011

buffers being optimized out?

I am a relative newby at VHDL coding.  I have defined an overall VHDL module which includes several components.  The components include 2-input and 6-input AND gates, inverters, registers, and buffers.  I have defined each of these components in its own VHDL file and successfully synthesized them.  I copied all the VHDL files from each of the components into the overall VHDL project file and added each to the overall project.  I did a successful synthesis on the overall VHDL project.

 

When I view the RTL schematic, though, it shows all of the components connected correctly except the buffers.  The wires (which should have been connected to the buffers) are just left floating... not connected to anything.

 

How do I put a buffer into a VHDL module?

How do I put a clock buffer into a VHDL module?

 

Thanks.

 

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Historian
Historian
3,435 Views
Registered: ‎02-25-2008

Re: buffers being optimized out?

I know you said you're a newbie, but why oh why are you creating components for primitives? The whole point of an HDL is to avoid instantiating every individual gate. Write code that describes the overall logic you want, and let the synthesis tool work out the details.

 

As for your specific questions.

 

a) There's never a need for a buffer  (like one channel of a 74xx541 bus buffer) inside an FPGA. The tools will optimize them away if you figure out how to instantiate them.

 

b) The correct Xilinx library component for a clock buffer is the BUFG, and you need to do the usual:

 

library  unisim;
use unisim.vcomponents.all;

 

at the top of your VHDL source. And the rule is that BUFG outputs can connect only to clock resources inside the FPGA. But having said that, in most cases you don't need to instantiate a clock buffer as the synthesizer is smart enough to recognize that a particular signal is used as a clock and the BUFG is inferred.

----------------------------Yes, I do this for a living.
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