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amritkumar2306
Visitor
Visitor
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Registered: ‎11-24-2020

can IP created by me, be implemented in a FPGA board

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I have written a verilog code for a digital modulator and sram. I have used readmemh to load some external data into the SRAM. Now i want to feed the data stored in the SRAM to the modulator. Can i do this by creating new IPs for the RAM and Modulator and connecting them through block diagram?? If yes afterwards can i implement the entire block in zc706 FPGA.

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kdeshwal
Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎11-12-2019

Hi @amritkumar2306 ,

Yes, you can create and package a custom IP.
Please check UG1118 (Creating and Packaging Custom IP User Guide)

Thanks,
Kuldeep

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Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
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kdeshwal
Xilinx Employee
Xilinx Employee
79 Views
Registered: ‎11-12-2019

Hi @amritkumar2306 ,

Yes, you can create and package a custom IP.
Please check UG1118 (Creating and Packaging Custom IP User Guide)

Thanks,
Kuldeep

-------------------------------------------------------------------------------------------------------------
Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
-------------------------------------------------------------------------------------------------------------

View solution in original post