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Visitor
Visitor
3,595 Views
Registered: ‎07-01-2017

cannot make VHDL instantiation of clock wizard

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Dear all

 

Here in Xilinx forum   (https://forums.xilinx.com/t5/Design-Entry/clock-wizard-v5-1-deliver-verilog-only/td-p/670664)  i have find out that Vivado 2015.4 Clock Wizard IP 5.2 can do VHDL instantiate. 

 

I attached print screen, please answer me, what i forget to do, and why I cannot make instantiate PLL to my project ?

 

 

VHDLPROBLEM.png
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Moderator
Moderator
3,638 Views
Registered: ‎09-15-2016

Hi @gabirmann

 

Please close the thread my marking the appropriate post which helped you with the resolution as "Accepted solution". This will help the future users.

 

Regards

Rohit

Regards
Rohit
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Adventurer
Adventurer
3,540 Views
Registered: ‎09-21-2016

Hello,

 

please go to the "IP sources" tab. There you can instantiation template of your desired language. VHDL or Verilog.

xilinx_help.JPG

Thank you

Rappy

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Moderator
Moderator
3,479 Views
Registered: ‎11-09-2015

Hi @rappysaha,

 

Post you code this way we can see what is missing.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor
Visitor
3,466 Views
Registered: ‎07-01-2017

OMG, that's work ! Thank you !

 

 

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Highlighted
Moderator
Moderator
3,639 Views
Registered: ‎09-15-2016

Hi @gabirmann

 

Please close the thread my marking the appropriate post which helped you with the resolution as "Accepted solution". This will help the future users.

 

Regards

Rohit

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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