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Agner
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Registered: ‎05-08-2020

clock wizard problems after upgrade to vivado 2020.3

After upgrading from Vivado 2020.1 to 2020.3 the clock wizard causes problems. Vivado crashed repeatedly when I tried to open the old clock generator. I had to delete the old clock generator and create a new one, using the clock wizard. Then I get the following problems:

  • The clock generator module is not found. I commented out this instance from the top module.
  • Warning: [Vivado_Tcl 4-1316] DCP is from an older vivado version, incremental synthesis won't be run
  • [Device 21-713] Unknown Tile Type, SLL, given for group, SLL
  • critical warning: [Designutils 20-1280] Could not find module 'clk_wizard_0'. The XDC file c:/_Public/ForwardCom/softCore/A2/A2.srcs/sources_1/ip/clk_wizard_0/clk_wizard_0_board.xdc will not be read for any cell of this module.
  • [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/bitstream_settings_a.xdc":50]
  • [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/bitstream_settings_a.xdc":51]
  • [Common 17-69] Command failed: 'E3' is not a valid site or package pin name. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/bitstream_settings_a.xdc":8]
  • [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/Nexys-A7-100T.xdc":108]
  • [Common 17-54] The object 'port' does not have a property 'PULLTYPE'. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/Nexys-A7-100T.xdc":114]
  • [Vivado 12-1411] Cannot set LOC property of ports, Site location (PS9_X0Y0) is not valid for the shape with the following elements:
    led0
    led0_OBUF_inst
    ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/Nexys-A7-100T.xdc":32]
  • Error: [DRC CIPS-2] Versal CIPS exists check - wdi: Versal designs must contain a CIPS IP in the netlist hierarchy to function properly. Please create an instance of the CIPS IP and configure it. Without a CIPS IP in the design, Vivado will not generate a CDO for the PMC, an elf for the PLM.
  • Error: [DRC NSTD-2] UNDEFINED I/O Standard issue: 37 out of 37 logical ports use I/O standard (IOSTANDARD) value 'UNDEFINED' or 'DIFF_UNDEFINED', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. NOTE: This DRC is READONLY and cannot be waived. Problem ports: digit7seg[7:0], lcd_data[3:0], lcd_e[1:0], segment7seg[7:0], lcd_rs, led0, led1, led12, led13, led14, led15, led2, led3, led4, led5... and (the first 15 of 19 listed).
  • [DRC UCIO-1] Unconstrained Logical Port: 37 out of 37 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: digit7seg[7:0], lcd_data[3:0], lcd_e[1:0], segment7seg[7:0], lcd_rs, led0, led1, led12, led13, led14, led15, led2, led3, led4, led5... and (the first 15 of 19 listed).
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4 Replies
Agner
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Registered: ‎05-08-2020

I have fixed some of the problems by fixing the names of the clock generator and its i/o names. Many other problems remain after updating to Vivado 2020.3:

  • [Common 17-69] Command failed: 'E3' is not a valid site or package pin name. ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/bitstream_settings_a.xdc":8].
    Why? Is the clock input pin no longer E3?
  • [Vivado 12-1411] Cannot set LOC property of ports, Site location (PS9_X0Y0) is not valid for the shape with the following elements:
    led0 led0_OBUF_inst ["C:/_Public/ForwardCom/softCore/A2/A2.srcs/constrs_1/new/Nexys-A7-100T.xdc":32]
    This line reads: set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports led0]
  • [DRC CIPS-2] Versal CIPS exists check - wdi: Versal designs must contain a CIPS IP in the netlist hierarchy to function properly. Please create an instance of the CIPS IP and configure it. Without a CIPS IP in the design, Vivado will not generate a CDO for the PMC, an elf for the PLM.
    What does this mean?
  • [DRC NSTD-2] UNDEFINED I/O Standard issue: 56 out of 57 logical ports use I/O standard (IOSTANDARD) value 'UNDEFINED' or 'DIFF_UNDEFINED', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. NOTE: This DRC is READONLY and cannot be waived. Problem ports: digit7seg[7:0], lcd_data[3:0], lcd_e[1:0], segment7seg[7:0], uart_txd_in, external_connected_x, lcd_rs, led0, led1, led12, led13, led14, led15, led2, led3... and (the first 15 of 38 listed).
    All pins have "IOSTANDARD LVCMOS33" in the .xdc file.
  • [Device 21-713] Unknown Tile Type, SLL, given for group, SLL
  • [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
  • [DRC 23-32] Ignoring request to add DRC rule check 'PDCNXA-3' to factory rule deck 'bitstream_checks'. Customization is not allowed for factory DRC rule decks. Please create a user copy of the factory DRC rule deck which can then be customized.
  • .. and many more warnings.

Please help!

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Agner
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Registered: ‎05-08-2020

The device XC7A100T is not listed as an option in Vivado version 2020.3. It only has XCVC and SCVM devices. It has changed my XC7A100T to XCVC1802. This explains the error messages. But why are the 7 series devices not listed in version 2020.3, and why has it changed my device to something else?

I can still open version 2020.1 and see that XC7A100T is still listed among supported devices, but version 2020.1 will not run after I installed version 2020.3. Both versions are installed on the same computer.

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micha_fa
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Participant
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Registered: ‎09-29-2011

Refering to the download page, Vivado 2020.3 is recommended only for Versal devices. So, the problems can be this odd version itself (even labeled 2020, but released 2021..- the art of versioning). I think you should keep 2020.1, go to 2020.2 or wait for another version.

Agner
Visitor
Visitor
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Registered: ‎05-08-2020

Thank you Micha

I would expect a more straightforward error message rather than just changing my device to some other device that causes tons of error messages and lots of headache.