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Contributor
Contributor
8,114 Views
Registered: ‎03-04-2009

clock wizard v5.1 deliver verilog only?

I have a vhdl-only version of modelsim-SE as we have only done vhdl designs so far. I discover that the output of clock wizard in vivado 2015.3 and 2015.4 is verilog only. I can work around this by using vivado 2015.2 using an older clock wizard to generate IP, but I wonder if it is a general path Xilinx is following in the future to not generate vhdl code for vhdl designs.

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2 Replies
Moderator
Moderator
8,108 Views
Registered: ‎01-16-2013

Re: clock wizard v5.1 deliver verilog only?

@svenn,

 

Clocking Wizard v5.1 does have both verilog and VHDL files. However from V5.2, the VHDL support for example design and simulation files has been removed.

http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf

 

http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_2/pg065-clk-wiz.pdf

 

In V5.2 has both verilog and VHDL instantiation template.

 

--Syed

 

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Contributor
Contributor
8,104 Views
Registered: ‎03-04-2009

Re: clock wizard v5.1 deliver verilog only?

You are right, I was too fast typing version numbers, it should have been 5.2 in my subject title. It is also the only version available in vivado 2015.4 install.

 

Xilinx care to elaborate on the move towards verilog only?

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