12-10-2015 04:31 AM
I have a vhdl-only version of modelsim-SE as we have only done vhdl designs so far. I discover that the output of clock wizard in vivado 2015.3 and 2015.4 is verilog only. I can work around this by using vivado 2015.2 using an older clock wizard to generate IP, but I wonder if it is a general path Xilinx is following in the future to not generate vhdl code for vhdl designs.
12-10-2015 05:16 AM - edited 12-10-2015 05:20 AM
Clocking Wizard v5.1 does have both verilog and VHDL files. However from V5.2, the VHDL support for example design and simulation files has been removed.
In V5.2 has both verilog and VHDL instantiation template.
12-10-2015 05:24 AM
You are right, I was too fast typing version numbers, it should have been 5.2 in my subject title. It is also the only version available in vivado 2015.4 install.
Xilinx care to elaborate on the move towards verilog only?