compiler directives in Top file for compiling ISE 13.1

[karthik.kishan@amd.com]

I am trying to use `define to select between modules that need to be instantiated during compile.

These defines seems to be working only for the top files but not for the instances/sub instances in the design.

In eg below i notice that CD U1 (X,Y,Z);  instance is always selected irrepetive of `define sim.

But if i place the define in Top1.v then AB U1 (X,Y,Z); is selected.

I am using ISE13.1 GUI for the same. How do i ensure that defines in top level is appilcabe to all the files and instances in the design?

File = Top_module.v

`define sim
module Top_module(
input A,
input B,
input C,
output Z
);

Top1 ff(A,B,Z);

endmodule

file = Top1.v

module Top1(
input X,
input Y,
output Z
);
`ifdef sim
AB U1 (X,Y,Z);
`else
CD U1 (X,Y,Z);
`endif

endmodule

[hemangd]

Hi karthik.kishan@amd.com,

Follow the steps as mentioned below to globally apply your define macro sim.

1. Go to the synthesis and right click on it and click on process properties (as shown below.)
2. It will open a popup as shown below and click on synthesis options. – make sure the option is set to advanced (as shown below in yellow ) so you will able to see -define verilog macros option where you have to write sim which is your macro. Then click on apply and then OK.
3. By doing this you will see that in your source hierarchy AB U1 module has been selected. (As shown below.)

 I hope this will resolve your query.