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Observer rutabagazuma
Observer
120 Views
Registered: ‎04-02-2019

design source remains after block diagram deletion

I have a block diagram from which I deleted a block 'SSDSP_SSDSPCh_wrapper_7_0'.   The block is gone from the diagram but remains in the sources viewer (see attachment).

Three other identical blocks were also deleted 'SSDSP_SSDSPCh_wrapper_(4,5,6)_0' without issue.

Vivado attempts to synthesize 'SSDSP_SSDSPCh_wrapper_7_0' when I synthesize the design.   The block fails synthesis.

How do I remove, completely, all references to this block?   There does not appear to be a way to do it from the sources viewer as 'remove file from project' is not an enabled option.

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2 Replies
Moderator
Moderator
68 Views
Registered: ‎11-09-2015

Re: design source remains after block diagram deletion

Hi @rutabagazuma 

Did you try to do reset output products for the BD. It should clear everything


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer rutabagazuma
Observer
56 Views
Registered: ‎04-02-2019

Re: design source remains after block diagram deletion

Resetting output products did not directly repair the problem.   At some point the tool dropped the references to the deleted IP.   I dont have an explanation as to what action brought vivado up to date though.

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