UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Scholar ronnywebers
Scholar
4,959 Views
Registered: ‎10-10-2014

do I need to re-synthesize after adding a new IO port constraint

Jump to solution

These are the steps concerned :

 

  • block design with some IP on it
  • I put some signal on an external port
  • I synthesize the design
  • open synthesized design
  • switch to IO layout
  • in the IO ports tab, I assign the external port to a package pin
  • when I hit save, this updates the target .xdc file with the new constraint

 

at this point Vivado says that the synthesis is out-of-date, but that you can choose to ignore this (to save time on unneeded re-synthesis?).

 

Question : is it ok to ignore this? and also, if I hit 'implement design', the synthesis run is executed anyway, so what's the point of the message that you can ignore this?

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
9,544 Views
Registered: ‎01-16-2013

Re: do I need to re-synthesize after adding a new IO port constraint

Jump to solution

@ronnywebers,

 

You dont need to synthesize the design again. When you click on more info next to out-of-date, you can do force up to date which will change the option to Synthesis complete.

Capture.PNG

 

Check page number 66 in below UG:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug892-vivado-design-flows-overview.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
4 Replies
Moderator
Moderator
9,545 Views
Registered: ‎01-16-2013

Re: do I need to re-synthesize after adding a new IO port constraint

Jump to solution

@ronnywebers,

 

You dont need to synthesize the design again. When you click on more info next to out-of-date, you can do force up to date which will change the option to Synthesis complete.

Capture.PNG

 

Check page number 66 in below UG:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug892-vivado-design-flows-overview.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
4,947 Views
Registered: ‎09-20-2012

Re: do I need to re-synthesize after adding a new IO port constraint

Jump to solution

Hi @ronnywebers

 

To add,

 

you can add a new XDC file, set the used_in property to Implementation and make it as target file.

 

This way if you change any pinout constraints and save the design, the constraints will be saved in to new XDC file and the synthesis will not go out-of-date. 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
Scholar ronnywebers
Scholar
4,941 Views
Registered: ‎10-10-2014

Re: do I need to re-synthesize after adding a new IO port constraint

Jump to solution

that's a great tip  @vemulad - if I read it correct that means that IO constraints are actually ignored by the synthesis proces? So as long as the .xdc concerned only contains IO constraints it's ok to set it to implementation only?

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
Moderator
Moderator
4,930 Views
Registered: ‎01-16-2013

Re: do I need to re-synthesize after adding a new IO port constraint

Jump to solution

@ronnywebers,

 

Yes, If the xdc only contains IO constraints then you can set it to implementation only.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------