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234 Views
Registered: ‎07-19-2019

document link

Provide document link where in which I can drag and pull the blocks and design as per my requirement. Is it possible to generate equivalent vhdl or verilog or c file of the block?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: document link

Are you talking about managing a block design using IPI? In that way,  you can take a look at the following doc:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug994-vivado-ip-subsystems.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug995-vivado-ip-subsystems-tutorial.pdf

You can create top-level HDL wrapper for the block design.

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