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m006
Voyager
Voyager
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Registered: ‎03-18-2008

does vivado has a synthesizeable axi bus monitor IP to recorde each axi transcation?

 
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hbucher
Scholar
Scholar
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Registered: ‎03-22-2016

@m006 You could use virtual i/o but it only helps in simulation

See lab 3

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug936-vivado-tutorial-programming-debugging.pdf

 

That said, you could possibly record every AXI transaction easy but the problem is how to store it - you would flood your storage very rapidly.

 

There are other ideas in the labs in this document too. 

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m006
Voyager
Voyager
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Registered: ‎03-18-2008

it depends on read/write trigger condition.

 

the data can be overwrite.

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hbucher
Scholar
Scholar
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Registered: ‎03-22-2016

The standard ILA debug will do it for you then

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dpaul24
Scholar
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Registered: ‎08-07-2014

does vivado has a synthesizeable axi bus monitor IP to recorde each axi transcation?

 

Directly answering your question, No.

 

Don't you think it is waste of silicon space? That's why, as you already know, BFMs are placed on the non-synth part of a design.

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