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Visitor nips
Visitor
4,381 Views
Registered: ‎05-11-2011

error please rectify:ConstraintSystem:59

 

UCF FILE
#  XUPV5-LX110T Evaluation Platform
Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20  |  IOSTANDARD=LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC = AH15  |  IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = E9  |  IOSTANDARD=LVCMOS33  |  PULLUP;
# LCD_FPGA_DB4
Net ROBB_IO_pin<1> LOC =T9 ;
Net ROBB_IO_pin<1> IOSTANDARD=LVCMOS33;
Net ROBB_IO_pin<1> PULLDOWN;
Net ROBB_IO_pin<1> SLEW=SLOW;
Net ROBB_IO_pin<1> DRIVE=2;
# LCD_FPGA_DB5
Net ROBB_IO_pin<0> LOC =G7 ;
Net ROBB_IO_pin<0> IOSTANDARD=LVCMOS33;
Net ROBB_IO_pin<0> PULLDOWN;
Net ROBB_IO_pin<0> SLEW=SLOW;
Net ROBB_IO_pin<0> DRIVE=2;
I AM getting this error and m not able to rectify it, please help::
ERROR:ConstraintSystem:59 - Constraint <Net ROBB_IO_pin<0> SLEW=SLOW;>
   [system.ucf(19)]: NET "ROBB_IO_pin<0>" not found.  Please verify that:
   1. The specified design element actually exists in the original design.

2. The specified object is spelled correctly in the constraint source file.

 

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2 Replies
Historian
Historian
4,376 Views
Registered: ‎02-25-2008

Re: error please rectify:ConstraintSystem:59

The signal in question doesn't exist in the design. Was it optimized away? Misspelled?

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
4,363 Views
Registered: ‎03-18-2008

Re: error please rectify:ConstraintSystem:59

I think this question would be better answered in the software forum...I will forward this for you
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