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Andrei
Visitor
Visitor
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Registered: ‎04-28-2020

error "common 17-70" help

Hi,

I am learning how AXI interface works and tried a small project with a top block design and where I use AXI GPIO and AXI Uartlite blocks to control the 4 LEDs from my Arty A7-35.

Project was created starting from board selection.

After successful Synthesis I get an error at Implementation phase. the log file states:

 

source TOP_LEVEL_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
Command: link_design -top TOP_LEVEL_wrapper -part xc7a35ticsg324-1L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_Core_0_0/TOP_LEVEL_Core_0_0.dcp' for cell 'TOP_LEVEL_i/Core_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_axi_gpio_0_1/TOP_LEVEL_axi_gpio_0_1.dcp' for cell 'TOP_LEVEL_i/axi_gpio_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_axi_uartlite_0_0/TOP_LEVEL_axi_uartlite_0_0.dcp' for cell 'TOP_LEVEL_i/axi_uartlite_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_c_counter_binary_0_0/TOP_LEVEL_c_counter_binary_0_0.dcp' for cell 'TOP_LEVEL_i/c_counter_binary_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_clk_wiz_0_0/TOP_LEVEL_clk_wiz_0_0.dcp' for cell 'TOP_LEVEL_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_xlconcat_0_0/TOP_LEVEL_xlconcat_0_0.dcp' for cell 'TOP_LEVEL_i/xlconcat_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_xlslice_0_0/TOP_LEVEL_xlslice_0_0.dcp' for cell 'TOP_LEVEL_i/xlslice_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_Core_0_0/TOP_LEVEL_Core_0_0.dcp' for cell 'TOP_LEVEL_i/Core_0'
11 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
ERROR: [Common 17-70] Application Exception: Failed to stitch checkpoint 'd:/Andrei/projects_hdl/AXI_UART_test/AXI_UART_test.srcs/sources_1/bd/TOP_LEVEL/ip/TOP_LEVEL_Core_0_0/TOP_LEVEL_Core_0_0.dcp' at cell 'TOP_LEVEL_i/Core_0'.
INFO: [Common 17-206] Exiting Vivado at Tue Mar 9 18:21:39 2021...

What is the issue???

 

Andrei

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syedz
Moderator
Moderator
106 Views
Registered: ‎01-16-2013

@Andrei 

 

Can you try generating the block design output products in non-OOC i.e "Global" mode and check if it passes?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug994-vivado-ip-subsystems.pdf#page=83 

 

--Syed

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