05-15-2019 03:01 AM
Hi All,
Tool : Vivado 2018.1
windows 1 : 64 bits
When I try to create/add a new ,it goes under Non-module Files even if there are no errors in the files.
please help me !!!
05-16-2019 02:19 AM
Hi @anis1133 ,
As per UG973 the supported version of windows 10 is fall creators update which is 1803. Please upgrade your windows to 1803 version.
DId you follow syed's comments as mentioned in last thread?
And is your PC's language set to english? If no please set and check.
05-15-2019 03:12 AM - edited 05-15-2019 03:15 AM
There seems to be a syntax error in the files. Can you show us the files in non-module reference? Also click on the highlited text (2) to see the critical warning.
Are you trying to create the wrapper for block design? You can right click on block design and select create HDL wrapper so that tool will generate the RTL file for your block design which will be picked as top module for synthesis and Implementation.
--Syed
05-15-2019 04:39 AM
05-15-2019 09:17 PM
Right click on design_1_wrapper.vhd file and select "Remove file from project". In the pop up box, select "Also delete the project local file/directory from disk"
Now Open the block design and run validation (Validate the design F6). If the validation is successful then you can create the wrapper by right-clicking on design_1.bd file and select "Create HDL wrapper".
Can you open the block design and show the block diagram?
--Syed
--Syed
05-15-2019 09:24 PM
Hi @anis1133 ,
If you are facing warnings while validation then it is recommended that you resolve those warnings before creating a wrapper.
Which Windows 10 version are you using?
05-16-2019 02:00 AM
05-16-2019 02:19 AM
Hi @anis1133 ,
As per UG973 the supported version of windows 10 is fall creators update which is 1803. Please upgrade your windows to 1803 version.
DId you follow syed's comments as mentioned in last thread?
And is your PC's language set to english? If no please set and check.
10-18-2019 02:12 AM
I had the same error.
My issue
The problem was that the "end component" was missed at the end of a component declaration at the beginning of the VHDL file.
component ps7_subsystem is port ( fixed_io_mio : inout std_logic_vector ( 53 downto 0 );
...
i_aux_reset : in std_logic ); end component ps7_subsystem; -- This line was missed
Xilinx employees!
Please fix it to show this missing line as syntax error (instead of heap error). I can help you to reproduce this issue, if its needed.
I use: