10-07-2019 11:55 AM
I am getting this error when I open my project in VIVADO 2018.3. The tool has a problem with my system verilog simulation file.
[filemgmt 20-742] The top module "TestBench_Top" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value.
Resolution: To switch to manual update order go to the Sources view, right-click on any node in the hierarchy and in the context menu select: 'Hierarchy Update' option 'No Update' or run the following Tcl Command: set_property source_mgmt_mode None [current_project] (which is the Manual Compile Order mode).
VIVADO says that I have a syntax error in the TestBench_Top file but I don't see it. What does "module used in incorrect context" mean?
The error at sys_clk_gen_ds says "Unexpected module instantiations outside module boundaries".
The error at initial begin says "initial used in incorrect context".
both header files are in the project and have no errors.