10-09-2018 08:05 AM
I have a design which I want to use in the PL part of a Zynq device. The easiest way to do this is adding the block as a module in the block diagram editor. The block has some sub-blocks, one of them is the xxv_ethernet:2.4 core. The problem I have is that this module does not support module reference, but I can add the same core, with the same settings in the block diagram as a seperate module. Is there a way where I can get my design in the block diagram editor (without compiling it as a separate IP) and not dragging all connections to the top-level to connect the core to my design in the block diagram?
10-09-2018 10:33 PM
Check if this post may answer your query.
10-10-2018 01:08 AM - edited 10-10-2018 01:17 AM
That thread is referencing another: https://forums.xilinx.com/t5/Design-Tools-Others/clock-wiz-dose-not-support-module-reference-in-vivado/m-p/852545#M11955 That one holds part of the info. But seems incorrect on the point of the SUPPORTS_MODREF property. This exists in stuff that can be added, and is absent in blocks that cannot. So the short answer to my question is sorry, but you can't. You'll need IP packager.
What I do not understand is why I am able to insert the (for me) same block in the block diagram as IP. What is the difference between the IP being instantiated in RTL which I want to use in the block diagram but cannot and add the "same" IP direcly in the block diagram. I use the exact same settings etc. so as far as I can see there is no difference, except that one works and another doesn't.
I am using Vivado 2018.1.
 I thought I might get it to work by adding the IP as a block to a block diagram, then generate a wrapper for that BD and then using that in my design it might work, since both are used in block designs, but that didn't work. I'll have to use the IP Packager. [/edit]
10-10-2018 09:33 AM
10-11-2018 02:03 AM - edited 10-11-2018 02:04 AM
No, I don't have further questions, but the question about the difference between the two "types" of IP still stands.
first "type": block diagram IP
second "type" xci file rtl IP
Why are they different even though the dialogs are the same and the ports are the same and the name is the same and the function is the same. What is different other than where you are allowed to use it?