cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
tchin123
Voyager
Voyager
541 Views
Registered: ‎05-14-2017

how to copy IP.xci to new project

I have created a new Vivado project and copy all my source file from another Project.

Is there a way to also copy all my IP over, does this involve copying only the .xci file, how is this perform within Vivado? there is menu for Add design and constraints but not for IP .xci

The IP consist of FIFO, BlockRAM, clk_wiz.

 

0 Kudos
9 Replies
richardhead
Scholar
Scholar
537 Views
Registered: ‎08-01-2012

 you can simply enter this into the tcl console:

read_ip <path>/your_ip.xci
syedz
Moderator
Moderator
465 Views
Registered: ‎01-16-2013

@tchin123 

 

You can  use "Add Sources" -->Add or create design sources option to add the xci file to new project. Click on add files:

image.png

 

For more details check the topic "Adding Existing IP to a Project" at UG896. Also, Chapter 6 should give you more understanding in working with IPs in Vivado:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug896-vivado-ip.pdf#page=33 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
dpaul24
Scholar
Scholar
461 Views
Registered: ‎08-07-2014

@tchin123 ,

It is pretty easy.

If your IP cores were generated with Core Container Enabled, then you just copy over the .xcix files to the new dir.

If the IPs did not have Core Container Enabled, then the main file would be .xci plus some associated files. Just copy all the files which are in the same dir along with the .xci files to the destination dir.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

tchin123
Voyager
Voyager
438 Views
Registered: ‎05-14-2017

What is the essential files that is required to be copy over to the new project. from Vivado, I would use the Add Source > Add or Create Design. sources  Traversing to the ../../source_1/ip/axi_ethernet_0 IP that are many files and folders as shown:. do I need all these file, folder or by copying the main file will bring them all in?

tchin123_0-1626444566811.png

 

0 Kudos
maps-mpls
Mentor
Mentor
435 Views
Registered: ‎06-20-2017

You can lead a horse to water....

*** Destination: Rapid design and development cycles *** Please remember to give internet points to those who help you here. ***
0 Kudos
dpaul24
Scholar
Scholar
435 Views
Registered: ‎08-07-2014

@tchin123 ,

Copy the complete directory axi_ethernet_0 to the new directory of your choice.

Then go to your project and add the .xci file for that IP core by the choosing,  Add Sources --> Add or create design sources option.

See the screenshot given above by @syedz .

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

tchin123
Voyager
Voyager
419 Views
Registered: ‎05-14-2017

Copy means, using "Window" (within PC window environment)  to copy the whole IP tree into the source_1 > IP directory

Then open Vivado and do a  ADD > Add Source and traverse and select the .xci file and Vivado will associate all the remaining file in the IP tree folder?

0 Kudos
maps-mpls
Mentor
Mentor
387 Views
Registered: ‎06-20-2017

See also UG896, particularly ch. 3.

*** Destination: Rapid design and development cycles *** Please remember to give internet points to those who help you here. ***
0 Kudos
dpaul24
Scholar
Scholar
337 Views
Registered: ‎08-07-2014

@tchin123 ,

Everything is very clear....what is it you do not understand?

Because I see that you are just "echo-ing" the previous replies and putting them as questions!

Do you have a problem understanding English language?

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.