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Visitor ksffj6eu
Visitor
6,063 Views
Registered: ‎07-11-2013

how to generate blk ram ip within verilog in vivado?

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Is it possible to generate blk ram ip within verilog using vivado?

i generated one within vhdl,but verilog is requied .How could i config the software tool?

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Xilinx Employee
Xilinx Employee
9,493 Views
Registered: ‎05-14-2008

Re: how to generate blk ram ip within verilog in vivado?

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Check the product buide of the block mem ip you're using to see if this ip provides Verilog language. If it doesn't the only option will be VHDL. If it does, you'll have Verilog source file of the IP as long as you have verilog set as the language in the project settings.

 

You can use "write_verilog" command to generate the verilog structural model of this IP to use in your project.

1. set the ip as top level

2. run synthesis in out_of_context mode

3. open synthesized design

4. run write_verilog command

 

Vivian

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Xilinx Employee
Xilinx Employee
9,494 Views
Registered: ‎05-14-2008

Re: how to generate blk ram ip within verilog in vivado?

Jump to solution

Check the product buide of the block mem ip you're using to see if this ip provides Verilog language. If it doesn't the only option will be VHDL. If it does, you'll have Verilog source file of the IP as long as you have verilog set as the language in the project settings.

 

You can use "write_verilog" command to generate the verilog structural model of this IP to use in your project.

1. set the ip as top level

2. run synthesis in out_of_context mode

3. open synthesized design

4. run write_verilog command

 

Vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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Historian
Historian
6,054 Views
Registered: ‎02-25-2008

Re: how to generate blk ram ip within verilog in vivado?

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@ksffj6eu wrote:

Is it possible to generate blk ram ip within verilog using vivado?

i generated one within vhdl,but verilog is requied .How could i config the software tool?


You should probably infer the memory rather than generating an IP core.

----------------------------Yes, I do this for a living.
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