I have made an AXI4-Lite Master for User IP, but I don't know the read logic.
I want to read with address in32 and output with out32.
I also found the explain in my file AzIP_AXI_Master_v1_0_M00_AXI.v
//------------------//Read example//------------------//Terminal Read Countalways @(posedge M_AXI_ACLK)beginif (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)last_read <= 1'b0;//The last read should be associated with a read address ready responseelse if ((read_index == C_M_TRANSACTIONS_NUM) && (M_AXI_ARREADY) )last_read <= 1'b1;elselast_read <= last_read;end/*Check for last read completion.This logic is to qualify the last read count with the final readresponse/data.*/always @(posedge M_AXI_ACLK)beginif (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)reads_done <= 1'b0;//The reads_done should be associated with a read ready responseelse if (last_read && M_AXI_RVALID && axi_rready)reads_done <= 1'b1;elsereads_done <= reads_done;end
You can create a new package IP with AXI peripherals in vivado (Tools > Create an package new IP > Create a new AXI4 Peripheral). This will generate template for the AXI4 interfaces