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Adventurer
Adventurer
4,769 Views
Registered: ‎06-27-2009

how to set the first state on a states machine made with flip-flops?

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hi, i have this schematic,

http://img31.imageshack.us/i/clipboard01nb.png/

 

which represent a states machine. Each flip-flop represents one state. But i need to set one of them as the first state. How can i set a flip-flop to start with true value, but only on the first cycle. I mean to make one flip-flop as initial state.

 

thanks

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Advisor eilert
Advisor
5,637 Views
Registered: ‎08-14-2007

Re: how to set the first state on a states machine made with flip-flops?

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Hi,

I guess he's probably doing some digital basics course, and doesn't know yet about HDLs.

We are using ISE/Modelsim with schematic entry for the same purpose here, which works fine.

 

So back to the original question:

You need to reset your FSM on power up.

Therfore you should use FDC (Flipflop with asynchronous clear) and FDP  (Flipflop with asynchronous preset).

 

You use the FDC for FFs that should start with '0' and FDP for those that schould start with '1'.

All are connected to a common Reset signal, which you have to activate once at the beginning.

Inside the FPGA there's a global Reset (GSR) available from the Startup block, which can be used.

 

 

For further information about resetting read this:

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

Have a nice synthesis

  Eilert

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Explorer
Explorer
4,760 Views
Registered: ‎07-14-2008

Re: how to set the first state on a states machine made with flip-flops?

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Just out of curiosity. Why are you modelling a FSM with schematic and not VHDL (or Verilog)? Isn't that like making things deliberately more complicated than necessary?
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Advisor eilert
Advisor
5,638 Views
Registered: ‎08-14-2007

Re: how to set the first state on a states machine made with flip-flops?

Jump to solution

Hi,

I guess he's probably doing some digital basics course, and doesn't know yet about HDLs.

We are using ISE/Modelsim with schematic entry for the same purpose here, which works fine.

 

So back to the original question:

You need to reset your FSM on power up.

Therfore you should use FDC (Flipflop with asynchronous clear) and FDP  (Flipflop with asynchronous preset).

 

You use the FDC for FFs that should start with '0' and FDP for those that schould start with '1'.

All are connected to a common Reset signal, which you have to activate once at the beginning.

Inside the FPGA there's a global Reset (GSR) available from the Startup block, which can be used.

 

 

For further information about resetting read this:

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

Have a nice synthesis

  Eilert

View solution in original post

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