10-08-2020 01:40 AM
I'm not English native language so please forgive my errors.
I need to band-pass filter 24 channel of data. Each channel is made by 500 samples and the filter length is 64 tapes.
Which is the best solution for this problem?
1) hand design a single fir filter and then use for-generate to copy the other 23s one
2) use the IpCore of FirFilter (that uses the AXI bus) and then for-generate the ip core
3) copy paste 24 times the ipCore in the System Generator
Any suggestion? Actually I don't know yet where the data will came from, maybe each channel will have it's block ram with the data inside, so I don't know if it's worth use the AXI or just a parallel communication.
Thank you for the help,
10-09-2020 08:58 AM
Bandwidth - what is the sample rate? Your design will look very different for Fs=10 MHz verses Fs=200 MHz.
A lot also depends on where your data is coming from, and going to. A FIR kernel is a simple design, there are many ways to do this and examples availble. The trickier stuff often is getting the data to the kernel(s), and getting the results out, in a timely manner.
In any event, yes use generate for() instead of cut/pasting 24 times.
10-09-2020 09:17 AM
xilinx FIR compiler IP core gives you many options to choose channel counter bandwidth number of coefficients and so on. Most of the times it uses the available FPGA ressources quite good. It supports 1024 interleaved channels. However it only supported 16 parallel paths.