10-06-2019 03:54 PM
I am facing an issue when trying to add some custom modules (.v files) into a block design created in Vivado, which I hope you can give me some guidance in this regard.
The thing is, I have cloned some .v files as my design source from this repository: https://github.com/hsharma35/dnnweaver2/tree/master/hardware/rtl
While following the steps for creating a project as instructed in https://github.com/hsharma35/dnnweaver2/tree/master/hardware, when I try to add the top-level cl_wrapper module, the module is shown in grey and cannot be selected and added as it says it is incompatible. I also see some (not all) submodules of this top-level module are considered to be incompatible, so I am guessing because of them being incompatible, the top-level module would not be compatible as well. But I do not know the reason(s) for a module being incompatible.
I have tested on both Vivado 2019.1, and 2018.3 (suggested by authors of custom modules in the mentioned link) and faced the same issue each time. I am attaching a screenshot of the error on Vivado 2018.3 as a reference:
10-07-2019 04:11 AM
Hi @amirhossein_esmaili .
Please check the files which are showing as incompatible for:
For detailed information on that pleas check page no.217 of below link:
10-08-2019 08:09 PM
Thank you very much for your answer.
I broke down the issue, and one problem I found was that mux_n_1.v, which is one of the modules needed for the synthesis of higher-level modules, is not compatible itself and thus cannot be added to the block design as it is (which probably causes the higher-level modules to be incompatible as well).
However, this module (mux_n_1) only uses mux_2_1.v as its submodule, where mux_2_1.v file exists and also is compatible and can be added to the Block Desing separately. For debugging this, what I tried to do was I created a new separate project in Vivado and only added mux_n_1.v and mux_2_1.v as source files, and attempted to synthesize the mux_n_1 in this new project. However, while mux_2_1 was still compatible, mux_n_1 is still incompatible and cannot be added to the block design.
I cannot figure the reason for this and I appreciate any help in this regard. For reference, I am attaching mux_2_1.v and mux_n_1.v files in case somebody wants to try this itself.