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haggaie
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Registered: ‎06-28-2016

ip_user_files/ipstatic filename conflicts

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Hi,

 

I'm using two IP cores (generates by Vivado HLS) in a project. For some reason HLS decided to generate the same Verilog filename in the two cores, but of course the content is completely different. When I add these IPs into the project (using read_ip on a pre-made XCI file) I get errors because only one of the files with the same name is placed in the ip_user_files/ipstatic directory and the other file is also needed.

 

Is there any way to let the simulation complete and letting the compilation find the needed files of each IP core in its own set of files?

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haggaie
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Registered: ‎06-28-2016

I found a workaround at the HLS level: there's a TCL command that adds a prefix to every module generated by HLS: 

config_rtl -prefix <prefix>

By using it and setting a different prefix for each HLS project I was able to solve the conflicts in Vivado's ipstatic directory. I still hope there's a better solution to make Vivado itself work correctly in these cases.

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hpoetzl
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Registered: ‎06-24-2013

Hey @haggaie,

 

Why not rename one of them so that they can be clearly distinguished?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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haggaie
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Registered: ‎06-28-2016
The files are autogenerated by HLS. If I take this approach, I'll have to rename them again and again on every change to the source C++ files.
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hpoetzl
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Registered: ‎06-24-2013

@haggaie,

 

The files are autogenerated by HLS.

Okay, so why not rename them in the HLS source?

Or are you telling me that your IP cores always result in identical names for the Verilog files regardless of the HSL/IP name?

 

Note: I know that it is most likely one of the many Vivado bugs, but I'm not sure why you don't work around the issue.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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haggaie
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Registered: ‎06-28-2016
I'm using the same C++ class to generate a sub module in two different projects. I can't rename the class because it is the same one. Also, I thought that the idea of using IP cores was to integrate IP created by different vendors. Do all vendors happen to choose different names for their internal modules?
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hpoetzl
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Registered: ‎06-24-2013

@haggaie,

 

Do all vendors happen to choose different names for their internal modules?

Probably not, but they will have different name domains for their IP.

 

Anyway, I agree that this is very likely a bug in Vivado, so let's wait for Xilinx to suggest a workaround or provide a fix.

I'd also suggest to create a simple test case which shows the problem so that it can be recreated easily.

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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haggaie
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What are name domains? Can I use them as well?

Sure, I'll upload a small test case.
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haggaie
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I'm attaching a minimal example here. The file hls/top.cpp contains the source for two HLS modules (top_a and top_b). They both have the same interface but a different implementation. The Verilog testbench vivado/tb.v integrates them both, with a tcl script to run the simulation (vivado/sim.tcl). An overall run.sh script generates the IP from the two HLS modules and tries to run the simulator. The result is as follows:

ERROR: [VRFC 10-426] cannot find port this_o on this module [/home/haggai/mwes/duplicate-filenames/vivado/prj.ip_user_files/ipstatic/hdl/verilog/top_b.v:38]
ERROR: [VRFC 10-426] cannot find port this_i on this module [/home/haggai/mwes/duplicate-filenames/vivado/prj.ip_user_files/ipstatic/hdl/verilog/top_b.v:37]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '0' seconds
INFO: [USF-XSim-99] Step results log file:'/home/haggai/mwes/duplicate-filenames/vivado/prj.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/haggai/mwes/duplicate-filenames/vivado/prj.sim/sim_1/behav/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

The error is because the top_b.v file is looking for its own operate.v sub-module, but instead the file in the ipstatic directory is the file belonging to top_a.

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haggaie
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Registered: ‎06-28-2016

I found a workaround at the HLS level: there's a TCL command that adds a prefix to every module generated by HLS: 

config_rtl -prefix <prefix>

By using it and setting a different prefix for each HLS project I was able to solve the conflicts in Vivado's ipstatic directory. I still hope there's a better solution to make Vivado itself work correctly in these cases.

View solution in original post

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