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Visitor
Visitor
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Registered: ‎10-10-2019

ise to vivado

I needed to open a ISE project in VIVADO, and there was an error at compile time,

[Synth 8-3493] module 'fpga_clk_gen' declared at 'G:/jun_fpga_test/TDC_MOTOR_FPGA/project_1/project_1.runs/synth_1/.Xil/Vivado-10332-Yct201907021144/realtime/FPGA_CLK_GEN_stub.vhdl:5' does not have matching formal port for component port 'clk_out2' ["G:/jun_fpga_test/TDC_MOTOR_FPGA/MotorController/CONTROLLER_TOP.vhd":100]

[Synth 8-285] failed synthesizing module 'MOTOR_CONTROLLER_TOP' ["G:/jun_fpga_test/TDC_MOTOR_FPGA/MotorController/CONTROLLER_TOP.vhd":43]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @wuxingkui

Share your test case with us for better understanding of it. 

Which Vivado version are you migrating to?

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor
Visitor
349 Views
Registered: ‎10-10-2019

vivado 2017.4

1.

FPGA_CLK_GENERATOR : FPGA_CLK_GEN
port map (CLK_IN1=>GCLK,
CLK_OUT1=>CLK_24MHZ,
CLK_OUT2=>CLK_1MHZ);

ERROR:

[Synth 8-3493] module 'fpga_clk_gen' declared at'G/FPGA_CLK_GEN_stub.vhdl:5' does not have matching formal port for component port 'clk_out2' 

2.

architecture BEHAVIORAL of MOTOR_CONTROLLER_TOP is
signal CLK_24MHZ : std_logic;
signal CLK_1MHZ : std_logic;
signal locked_div : std_logic_vector (1 downto 0);
signal MOTOR_SPEED_VALUE : std_logic_vector (9 downto 0);
signal NET_SPEED_DETECT_DONE : std_logic;
signal SPI_TRIGGER : std_logic;
signal SSN_DUMMY : std_logic;
signal SPI_DIN : std_logic_vector (15 downto 0);
component FPGA_CLK_GEN
port ( CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic);
end component;

ERROR:

[Synth 8-285] failed synthesizing module 'MOTOR_CONTROLLER_TOP' 

I dont know what happened, this project works well in ISE, but in VIVADO, there are some errors.  

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Highlighted
Moderator
Moderator
327 Views
Registered: ‎03-16-2017

Hi @wuxingkui

Check FPGA_CLK_GEN_stub.vhd that clk_out2 input port is present or not. If not present, please define the clk_out2 port in the original file.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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