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Newbie rdickerson
Registered: ‎05-02-2010

low latency FIFO

I'm using a FIFO to bridge two phase-locked clock domains (in a Virtex4); I'm performing exactly one enqueue and one dequeue every clock cycle.  I want to minimize the latency going through this FIFO.  Is it safe to tie the FIFO read enable to '1', knowing that the first few samples I get after reset will be garbage?  I know the V4 FIFO16 has some issues with the empty flag getting into an incorrect state, but what if I'm only intereseted in the read data?

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