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benmishoe
Adventurer
Adventurer
801 Views
Registered: ‎10-19-2012

missing ports when I package my own IP

Following various Xilinx tutorials, I've created a custom IP block that performs a modular exponentiation function through the Vivado wizard.  Rather than run the math function at the S_AXI_ACLK frequency, I want to have a separate clock input so I can run it at a frequency of my choosing separate from the AXI_ACLK rate.

Hazving created the IP block, my Sources window shows:

mod_exp_function_v1_0.v which instances mod_exp_function_v1_0_S00_AXI.v

In the S00_AXI.v instance, I added a port input wire i_clk_mod_exp and then I added my logic.

In the mod_exp_function_v1_0_S00_AXI.v file, I added the same port, and then I connected it to my instance:

.i_clk_mod_exp(i_clk_mod_exp),

I synthesized with no errors and packaged the IP.  However, my i_clk_mod_exp port is not listed as one of the ports on the "Ports and Interfaces" packaging step, nor does it show up in the Customization GUI page.  Furthermore, if I exit the IP editor and place my IP block on my main block diagram, this clock port isn't visible.

I've searched online for other reports of this, the only answer I found in the forum was that it has to be declared as a wire, but as you can see above I did declare mine as a wire.  Can someone point me in the right direction?  thanks in advance

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surajc
Xilinx Employee
Xilinx Employee
773 Views
Registered: ‎01-30-2019

@benmishoe 

can you show us the hierarchy and the input-output ports of the HDL files

-Suraj

 

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benmishoe
Adventurer
Adventurer
767 Views
Registered: ‎10-19-2012

I have an update on this....I eventually got the port to show up, but only after I went to the port customization tab and then clicked "import IP ports".  This became a big headache as I have to re-import even all the default AXI ports that were created by default when I made a new IP and assign them accordingly.

I was following a digilent tutorial (https://bit.ly/2IdbMDd), but in their example, simply adding the ports to the RTL caused them to show up in the symbol.  Is there any reason the 'import' step was necessary for me?  Is there any Xilinx tutorial where a port is added (so far I haven't found one)?

Thanks in advance...

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