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tchin123
Voyager
Voyager
311 Views
Registered: ‎05-14-2017

mixing verilog code with vhdl declaration issue

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I have created an IP example design from vivado IP core but some of the supporting files are in verilog,To use them, I created component declaration and instantiation from it into my VHDL design.

I believed Vivado is capable of mixing verilog and vhdl. Since some of the supporting file is in verilog and the my component instantiation is in VHDL, I am getting error on all the ports: and it complains that the "axi_ethernet_0_clocks_resets" is not a component.  one of these port issue is as shown:

<The direction of the input "clk_in_p"is not explicitly declared. >

Any idea how to resolve this issue?

Here is the sample verilog from IP Design Example:

tchin123_0-1601937388649.png

and here is my vhdl component declaration and instantiation shown below. the RED line is the error below

tchin123_1-1601937429063.png

tchin123_2-1601937446393.png

Thanks

 

 

 

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shantmoses
Contributor
Contributor
298 Views
Registered: ‎07-01-2008

Port names are not consistent between the module and component declaration. For example axi_lite_resetn in the module and the instance but its axi_lite_rstn in the declaration.

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shantmoses
Contributor
Contributor
299 Views
Registered: ‎07-01-2008

Port names are not consistent between the module and component declaration. For example axi_lite_resetn in the module and the instance but its axi_lite_rstn in the declaration.

View solution in original post

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