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Newbie
Newbie
5,018 Views
Registered: ‎01-29-2011

need help

hi all

i must design decimation filter in Hspice

i need a block diagram for decimation filter that it use for sigma-delta A/D

pleas give mee a block diagram of decimation filter whit transistor that i can use it in Hspice

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Instructor
Instructor
5,016 Views
Registered: ‎07-21-2009

i must design decimation filter in Hspice

i need a block diagram for decimation filter that it use for sigma-delta A/D

pleas give mee a block diagram of decimation filter whit transistor that i can use it in Hspice

Is this a school project? How many FPGA designs have you successfully completed?

Do you have a solid understanding of decimation filters and A/Ds?  Does your A/D have an anti-aliasing filter on its input?

 

HSPICE is the wrong tool for simulating digital filters.  Matlab would be a good choice, or you could write your own emulator in C or some other programming language.

 

This is primarily an FPGA design forum, to assist with understanding Xilinx FPGAs and Xilinx design tools.  If you already know what type of filter you need (how many taps, what coefficients, frequency response, etc,) we could help you with various filter implementation assist tools which are specifically written for FPGA design.  These tools will greatly simplify filter implementation, but you need to be able to tell the filter tool what you need.

 

Perhaps if you described your design problem with a bit more detail, we might be able to point you in the right direction.

 

- Bob Elkind

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Historian
Historian
4,964 Views
Registered: ‎02-25-2008

 


@p_esfehani wrote:

hi all

i must design decimation filter in Hspice

i need a block diagram for decimation filter that it use for sigma-delta A/D

pleas give mee a block diagram of decimation filter whit transistor that i can use it in Hspice


So, what made you think that the Xilinx FPGA forum would have any useful information about Hspice?

 

----------------------------Yes, I do this for a living.