09-11-2014 09:15 AM
Still on the path of multiple BDs synthesized separately, then aggregated into a top.
When I open the synthesized top for analysis, I get the following warning, which I am sure will be reported as an error during placement. Can please someone tell me why am I getting it?
[Project 1-486] Could not resolve non-primitive black box cell 'bd_displayport_bd_displayport_bd_displayport_bd_displayport_fifo_generator_v12_0' instantiated as 'U0' [/home/IGNIS/vmuravin/projects/orchestra/vivado/phoenix/phoenix5/phoenix5/phoenix5.srcs/sources_1/ipshared/www.ignisinnovation.com/displayport_sink_v1_0_v1_0/e32de0c9/src/displayport_sink_4x5p4/displayport_v5_0/hdl/sink/displayport_v5_0_rx_vid_fifo.vhd:2]
09-11-2014 09:34 AM
Thanks Yash. Our case seems to be both these AR#.
If there is a black_box in the DisplayPort core, which is an encrypted core, I should not be worried then? This warning will not yield place/route failure, correct? I am asking because I have not see anything this when using full-chip single-BD synthesis.
09-11-2014 11:13 AM
And I finally got to the place/route error, see it below. How do I solve it then? The AR# provided are not answering this problem.
NOTE: This is an early beta release of the DisplayPort 5.0 core that would be officially out with 2014.3 (very soon I suppose).
Is there any chance that this FIFO generator 12.0 is not present in some sort of libraries referenced internally by the tool (such as unisims for synthesis etc) ? Why we see no such issues when we synthesize a full-chip canvas? SOS please.
[Opt 31-30] Blackbox inst_bd_displayport_wrapper/bd_displayport_i/inst_displayport/inst/inst/support_inst/core_top_inst/dport_link_inst/displayport_v5_0_rx_link_inst/displayport_v5_0_rx_main_inst/gen_user_modules.displayport_v5_0_rx_user_inst/displayport_v5_0_rx_user_fifo_lane_0/displayport_v5_0_rx_vid_fifo_inst/U0 (bd_displayport_bd_displayport_bd_displayport_bd_displayport_fifo_generator_v12_0) is driving pin I1 of primitive cell inst_bd_displayport_wrapper/bd_displayport_i/inst_displayport/inst/inst/support_inst/core_top_inst/dport_link_inst/displayport_v5_0_rx_link_inst/displayport_v5_0_rx_main_inst/gen_user_modules.displayport_v5_0_rx_user_inst/displayport_v5_0_rx_user_fifo_lane_1/displayport_v5_0_rx_vid_fifo_inst/dual_lane_sel_i_32. This blackbox cannot be found in the existing library.
09-11-2014 11:18 AM
09-12-2014 06:41 AM
Yash, Deepika, and everyone else,
Would you please suggest a solution? These AR# are very educational but they offer no solution. What do I do in this case?
09-12-2014 08:26 AM
09-15-2014 10:02 AM
Yash and everyone else,
I wanted to try bypassing this by unsetting the OOC on the DisplayPort BD, i.e.
delete_fileset [get_filesets bd_displayport] -merge [current_fileset]
Where the [current_set] returned sources_1
This left me with 11 OOC BDs and 1 In-context BD while a top HDL wrapper wraps all the BDs' wrappers.
Then I ran the synthesis and I got the same error but this time any single interface the DisplayPort BD interfaces with reporting this error, i.e. the first one looks like this:
[Opt 31-30] Blackbox inst_bd_displayport_wrapper/bd_displayport_i (bd_displayport) is driving pin I0 of primitive cell inst_bd_testbus_mux_wrapper/bd_testbus_mux_i/inst_testbus_mux/inst/inst_testbus_mux_cfg/chipscope1_gen.chipscope1_tbus_i_2. This blackbox cannot be found in the existing library.
Is there any way I am missing some sort of a library pointer etc (ISE speaking, -sd) or this is still the same problem with encrypted netlists?
Thanks and BR
09-17-2014 01:30 PM
I made another experiment and it may or may not have solved this problem.
Basically, I moved the DisplayPort IP into another BD canvas that has Microblaze and associated stuff. So, probably because there are other IPs on that BD that do use the FIFO generator, the DisplayPort resolution did not report anything, and opt_design actually finished to the end.
I do have next-step problems during place_design and this will be taken as another posting but it would be nice if Xilinx would address this one.
Thanks a lot