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Explorer
Explorer
627 Views
Registered: ‎09-08-2014

p7 axi peripheral

Hi

I have implemented a design. It was working ok. I added some debug and now when I validate the design I get an error with the p7 axi peripheral. What makes no sense to me is there is no way for me to make this connection. This is buried within the block. See the attached images.

Pete

 

 

p7 axi peripheral.jpg
p7 axi peripheral_2.jpg
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4 Replies
Xilinx Employee
Xilinx Employee
619 Views
Registered: ‎05-22-2018

Hi @pcaddick ,

Which version of Vivado are you using?

Can you try  deleting the AXI interconnect module and then adding the IP again ? and see if resolves the issue.
This fixed this error in some previous cases.

Thanks,

Raj

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Explorer
Explorer
616 Views
Registered: ‎09-08-2014

I'm using 2017.4. Yes, I can do that but its a pain. Isn't there some way of making the tool sort it out.

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Explorer
Explorer
608 Views
Registered: ‎09-08-2014

I tried replacing it but I still get the same error.

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Explorer
Explorer
606 Views
Registered: ‎09-08-2014

Not only that but the replacement is even worse!!!

p7 axi peripheral_3.jpg
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