07-25-2016 06:56 PM
I have design based on the following XAPP: http://www.xilinx.com/support/documentation/application_notes/xapp1171-pcie-central-dma-subsystem.pdf
I would like to package the portion of the block diagram which is called "pcie cdma subsystem". This is a hierarchy of IP instantiated in the block diagram in addition to zynq_PS and some reset blocks. I would like to package just this cell. Is it possible to do this? Any suggestions are welcome.
07-25-2016 09:34 PM
I assume that pcie cdma subsystem is also a block design which is present inside the top level block design. If this is true then you can use write_bd_tcl command to export the TCL and use it to create block design in the project. Once this is done you can package the block design.
07-25-2016 09:38 PM - edited 07-25-2016 09:59 PM
Actually both projects are created from bd.tcl files and I decided to copy parts of the bd.tcl to a file to source it in the target bd.tcl (or after sourcing the target bd.tcl). I am not following the suggested/usual methods to closely but it seems to work for me. These days I can even modify the bd.tcl manually to do design.