I have a RTL block in a general block design. I want group pins into a bus, like is done automatically when I put together a AXI stream group. The AXI stream group and associated clock automatically group together.
I have actually instantiated the DDR4 MIG in RTL and I have the c0_ddr4 pins listed. I cannot figure out how to group them together to allow simple bus connection to the ddr4_sdram pin group in the block design.