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Visitor boyerkg
Visitor
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Registered: ‎08-18-2017

pin group rtl block design

Hi All,

I have a RTL block in a general block design.  I want group pins into a bus, like is done automatically when I put together a AXI stream group.  The AXI stream group and associated clock automatically group together.

I have actually instantiated the DDR4 MIG in RTL and I have the c0_ddr4 pins listed.  I cannot figure out how to group them together to allow simple bus connection to the ddr4_sdram pin group in the block design.

Regards,

Keith

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Moderator
Moderator
160 Views
Registered: ‎11-09-2015

Re: pin group rtl block design

Hi @boyerkg 

You might want to have a look at the section Inferring Control Signals in a RTL Module in PG994 from p226. This should be what you are looking for.

PS: In vivado the name of the interface for DDR is VLNV xilinx.com:interface:ddrx_rtl:1.0

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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