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Visitor jweintr
Visitor
5,900 Views
Registered: ‎01-07-2016

port order in ip package gui

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Hi all,  this seems like it oughta be a no brainer (and hoping the answer is still a "duh!" :), but I've been through the manuals and answer notes and google, and still finding no references ...

 

To wit:

 

I package an IP project, the top level of which is a VHDL source file, and when the GUI symbol for the package is presented, all the input (left side) and output (right side) ports are presented in alphabetical order.

 

How can I change this?  (I'd like them to appear in the order provided in my "entity" block.)

 

Thanks, and all the best,

 

Joe

 

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Visitor jweintr
Visitor
10,654 Views
Registered: ‎01-07-2016

Re: port order in ip package gui

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Ah, thanks for the follow up, Syed!

 

So actually, I was using "package project" (rather than BD), all along - think I'd seen that in a previous forum post.

 

However, I just did create a small RTL example (no BD needed), and recreated the issue - and its solution.

 

It turns out that after I modified the VHDL code to change the port ordering, I was re-packaging the project by clicking on "Package IP" from the "Project Manager" section in Flow Manager, and then in the Config GUI, clicking on the selection to Update based on the Config Wizard.  As shown in the attachment  (I hope! ... haven't tried attachments til now:>), this did not update the port order in the schematic symbol to corresponding to the modified VHDL code.

 

However, I just found that, if instead, I select "Tools->Create and Package New IP ..." from the main menu bar, then the Customization appears to start from scratch, and now the ports appear, as desired, in the order presented in the VHDL entity block.

 

That solves my issue, though I am wondering whether this difference in behavior between the two methods is intentional for some reason, or otherwise?

 

Again, many thanks!

 

Joseph

 

 

 

package_port_order_gui.PNG
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6 Replies
Moderator
Moderator
5,893 Views
Registered: ‎01-16-2013

Re: port order in ip package gui

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@jweintr,

 

I just checked on an example design in Vivado 2016.1 and I do not see the ports in alphabetical order for the VHDL module.

The order is according to the entity port declaration.

Capture.JPG

 

--Syed

 

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Visitor jweintr
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5,873 Views
Registered: ‎01-07-2016

Re: port order in ip package gui

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@syedz,   many thanks for the speedy reply, and checking this out on my behalf.

 

I've used the packager in the past, and this was the first time I had seen this particular phenomenon.

 

So now I think I have a better picture of what happened here.  The full story is:

 

1) I had a block diagram containing several RTL modules wired together.

 

2) I wanted to package this, but (as seen in other threads), I discovered that module references not yet supported in the package.

 

3) Therefore, I took the vhdl wrapper created from the BD and used it as the top level of a VHDL-only project to feed to the packager.

 

4) BUT, the ports as written to the ENTITY block of the bd wrapper were given in alphabetical order, so that's what the packager initially saw.

 

5) I then modified the top level wrapper to give the ports in the desired order, but apparently that had no further effect, once the gui order had been determined.

 

6) So now, after your response, I just took the same VHDL files - including my modified top level wrapper - and put them into a new project, where they packaged just fine, with the ports all given in the order I expect.

 

Perhaps there is a command or operation I could have done to eliminate the need for copying and recreating the project in step (6) above?

 

Thanks again,

 

Joe

 

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Moderator
Moderator
5,836 Views
Registered: ‎01-16-2013

Re: port order in ip package gui

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@jweintr,

 

After editing the wrapper file, when you package the IP try selecting Package your current project as shown below:

 

Capture.JPG

 

If you select package the block design from current project then the wrapper file is regenerated there by overwiting the modification.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Moderator
Moderator
5,815 Views
Registered: ‎01-16-2013

Re: port order in ip package gui

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@jweintr,

 

Did you try the suggestion mentioned in my previous post?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Visitor jweintr
Visitor
10,655 Views
Registered: ‎01-07-2016

Re: port order in ip package gui

Jump to solution

Ah, thanks for the follow up, Syed!

 

So actually, I was using "package project" (rather than BD), all along - think I'd seen that in a previous forum post.

 

However, I just did create a small RTL example (no BD needed), and recreated the issue - and its solution.

 

It turns out that after I modified the VHDL code to change the port ordering, I was re-packaging the project by clicking on "Package IP" from the "Project Manager" section in Flow Manager, and then in the Config GUI, clicking on the selection to Update based on the Config Wizard.  As shown in the attachment  (I hope! ... haven't tried attachments til now:>), this did not update the port order in the schematic symbol to corresponding to the modified VHDL code.

 

However, I just found that, if instead, I select "Tools->Create and Package New IP ..." from the main menu bar, then the Customization appears to start from scratch, and now the ports appear, as desired, in the order presented in the VHDL entity block.

 

That solves my issue, though I am wondering whether this difference in behavior between the two methods is intentional for some reason, or otherwise?

 

Again, many thanks!

 

Joseph

 

 

 

package_port_order_gui.PNG
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Observer alexkroh
Observer
287 Views
Registered: ‎04-25-2015

Re: port order in ip package gui

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I changed the order in component.xml. It was tedious, but it worked.

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