generated a fifo with the “Fifo generator 5.1” which should be used in a “xcvlx50”
device. It has independent read/ write clocks and is realized with distributed
I have is shown in the added picture. At “1” the first data is written to the
fifo after initial reset. But sometimes goes wrong with the “rd_data_count” at
position “2”. Instead of showing “00” or “01” I can found “7f”. This only
happens directly after the reset of the fifo. After that everything is fine as
shown in “3”.
Read Data Count: This bus indicates the number of words available for reading in the FIFO. The count is guaranteed to never over-report the number of words available for reading, to ensure that the user does not underflow the FIFO. The exception to this behavior is when the read operation occurs at the rising edge of RD_CLK, that read operation will only be reflected on RD_DATA_COUNT at the next rising clock edge.
If this is the same for v5.1 it explains the behaviour of your simulation.