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Observer karthiii
Observer
8,674 Views
Registered: ‎08-13-2008

quick port mapping and Variable usage

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I have one more doubt on variable usage and if get a solution ASAP it could help me move to next stage

 

i have attached the code for your reference

 

in which I have a component used 8 times resembling ch0 to ch7,

 

now I have to port map it to the top module but the top module has a 32 bit out port and my components have 4 bit out port

each time I use the component in port map I have to specify

like CH0 component connects to bit 3 to 0 of top module

            CH1 component connects to bit 7 to 4 of top module

CH2 component connects to bit 11 to 8 of top module

And so on,

 

Now this becomes difficult in big hdl codes and are subject to human errors

 

So what I did is, I tried to use variables, and re wrote the program like

 

 

i <= 0;

Ch0 :  xxxxxx

port map (

                        xxxx(i+ 3 downto i);

 

i <= i + 1;

Ch1 :  xxxxxx

port map (

                        xxxx(i+ 3 downto i);

 

i <= i + 1;

Ch2 :  xxxxxx

port map (

                        xxxx(i+ 3 downto i);

 

i <= i + 1;

Ch3 :  xxxxxx

port map (

                        xxxx(i+ 3 downto i);

 

 

is this correct or is there any better way

and first of all can a variable be used outside a process, because here its reporting errors, like variable i is not static

later it said only shared variables can be used outisde process..

 

kindly help

 

 

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Scholar drjohnsmith
Scholar
10,705 Views
Registered: ‎07-09-2009

Re: quick port mapping and Variable usage

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Hi

 

stop writing C code is a good place to start.

 

your using vhdl, which is a hard ware description language,

 

   so look at the generate statment,

 

 

Tags (1)
7 Replies
Observer karthiii
Observer
8,670 Views
Registered: ‎08-13-2008

Re: quick port mapping and Variable usage

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example code

 

-- Design Name:
-- Module Name:    port_map_autoinc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:     ISE 12.4
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- optional Lib if you need   -> kk
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
library work;
use work.karthik_vhdlib.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity port_map_autoinc is
    Port ( dout : out  STD_LOGIC_VECTOR (15 downto 0));
end port_map_autoinc;

architecture Behavioral of port_map_autoinc is

component usr_inst is
    Port ( cons_out : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

shared variable i     :    integer := 1;

begin


    u1:    usr_inst
    port map ( cons_out => dout(i + 3 downto i));

--    u2:    usr_inst
--    port map ( cons_out => dout(7 downto 4));
--
--    u3:    usr_inst
--    port map ( cons_out => dout(11 downto 8));
--
--    u4:    usr_inst
--    port map ( cons_out => dout(15 downto 12));


end Behavioral;



----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- optional Lib if you need   -> kk
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
library work;
use work.karthik_vhdlib.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity usr_inst is
    Port ( cons_out : out  STD_LOGIC_VECTOR (3 downto 0));
end usr_inst;

architecture Behavioral of usr_inst is

begin
    
        cons_out    <= X"2";
    
end Behavioral;


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Scholar drjohnsmith
Scholar
10,706 Views
Registered: ‎07-09-2009

Re: quick port mapping and Variable usage

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Hi

 

stop writing C code is a good place to start.

 

your using vhdl, which is a hard ware description language,

 

   so look at the generate statment,

 

 

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Observer karthiii
Observer
8,663 Views
Registered: ‎08-13-2008

Re: quick port mapping and Variable usage

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hi

i agree with your point ,

 

but if a coding technique can reduce code development time , why cant it be considered,

 

i thought of using generate statement

but i belive there also i have to manualy type , am i correct ?

 

3 downto 0

7 downto 4

11 downto 8

15 downto 12

 

this takes time to write code since i have to type 64 lines in 7 of my modules and keeping in mind that i dont leave a human error

 

 

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Scholar drjohnsmith
Scholar
8,658 Views
Registered: ‎07-09-2009

Re: quick port mapping and Variable usage

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Ok, 

 

good to try new ideas, 

 

but generate is the way to do it,

 

cut stick paste,

 

or seperate the module out, into a seperate entity, and pass the paramiters in,

 

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Scholar drjohnsmith
Scholar
8,657 Views
Registered: ‎07-09-2009

Re: quick port mapping and Variable usage

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Oh, 

 

and use the generic map to pass down to the entity the paramiter of the port width,#

 

does that make sence ?

 

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Instructor
Instructor
8,655 Views
Registered: ‎08-14-2007

Re: quick port mapping and Variable usage

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Or write it in Verilog and use an array of instances.  Then you can just have

 

wire [15:0] dout;

 

foo user_inst[3:0]

(

  .dout (dout), // port dout of individual instance of foo is 4 bit "slice" of 16-bit dout

  ...

);

 

-- Gabor

-- Gabor
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Historian
Historian
8,646 Views
Registered: ‎02-25-2008

Re: quick port mapping and Variable usage

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@drjohnsmith wrote:

Hi

 

stop writing C code is a good place to start.

 

your using vhdl, which is a hard ware description language,

 

   so look at the generate statment,

 

 


This is the correct answer.

 

----------------------------Yes, I do this for a living.
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