UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
112 Views
Registered: ‎05-30-2018

"Add Module to Block Design" option is desactivated

Jump to solution

Hello,

While trying to instantiate my VHDL design in Block Diagram, I see that option "Add Module to Block Design" is desactivated.

Any suggestions ?

Thanks

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
53 Views
Registered: ‎11-09-2015

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Hi @pavel_47 ,

The used in implementation option is a different thing. And it does not make much sense for sources files as you are not using them directly for implementation (you usually have the netlist). I am not sure why there is a difference between verilog and VHDL files. But if you are woried about this you can always add the option even for VHDL file:

set_property USED_IN {synthesis simulation implementation} [get_files <path>/file.vhd]

It makes more sense for xdc files.

To come back on the Add module feature, I made a quick test files in VHDL and I can import it as module:

VHDL.JPG

 

Note that this is a VHDL file not a VHDL2008. I do not think VHDL2008 will work as top level but can be integrated into another file. This is probably what you are experiencing

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
7 Replies
Explorer
Explorer
102 Views
Registered: ‎05-30-2018

Re: "Add Module to Block Design" option is desactivated

Jump to solution

It seems that this option is active only for Verilog modules.

0 Kudos
Explorer
Explorer
101 Views
Registered: ‎05-30-2018

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Also there is no "Usied in Implementation" option for VHDL blocks ... only "Used in Synthesis", "Used in Simulation".

Verilog blocks have all 3 options.

0 Kudos
Moderator
Moderator
74 Views
Registered: ‎11-09-2015

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Hi @pavel_47 ,

It would be helpful if you mention what version you are using.

Then if you have a test case to share it would also be helpful.

With vivado 2018.3, you should be able to add a module from VHDL or Verilog sources. But in some case, the module might be incompatible. For example:

  • Files that have syntactical errors
  • Modules with missing sources
  • Module definitions that contain or refer to an EDIF netlist, a DCP file, another block design, or unsupported IP

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Explorer
Explorer
67 Views
Registered: ‎05-30-2018

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Hi Florent,

Thanks.

I use 2018.3.

There are no any syntax errors ... at least any vhdl module was imported without errors.

Nevertheless I've found a workaround: instantiate vhdl in verilog and then add verilog in block diagram.

This way it worked.

What about abscence "Used in implementation" option for vhdl modules ?

Probably if this option could be enabled in some way, vhdl modules also can be added in block diagram ?

Regards.

Pavel.

0 Kudos
Moderator
Moderator
54 Views
Registered: ‎11-09-2015

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Hi @pavel_47 ,

The used in implementation option is a different thing. And it does not make much sense for sources files as you are not using them directly for implementation (you usually have the netlist). I am not sure why there is a difference between verilog and VHDL files. But if you are woried about this you can always add the option even for VHDL file:

set_property USED_IN {synthesis simulation implementation} [get_files <path>/file.vhd]

It makes more sense for xdc files.

To come back on the Add module feature, I made a quick test files in VHDL and I can import it as module:

VHDL.JPG

 

Note that this is a VHDL file not a VHDL2008. I do not think VHDL2008 will work as top level but can be integrated into another file. This is probably what you are experiencing

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Explorer
Explorer
46 Views
Registered: ‎05-30-2018

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Yes, it was th case: VHDL module was VHDL2008.

Thanks !

0 Kudos
Moderator
Moderator
44 Views
Registered: ‎11-09-2015

Re: "Add Module to Block Design" option is desactivated

Jump to solution

Hi @pavel_47 ,

For you information: The limitation is mentioned in chapter 2 of UG1118:

VHDL2008.JPG

You need a top level wrapper if you need to use VHDL2008 or systemVerilog.

IP Packager is running under the hood when you use the import feature option

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos