03-12-2009 04:36 AM
It seems, I don't understand the exact design flow to create an SDRAM controller,
as I get above mentioned Error message:
I start Coregen:
-> Create New Project
In the Part tab
- Spartan 3A and 3AN
- speed grade -4
In the Generation Tab:
- Flow: Design entry Verilog
- Flow Settings ISE
other settings default
In the Advanced Tab:
- no changes to default values
Now I save the project (just in case)
Memories & Storage Elements -> Memory Interface Generation
I double click on MIG (2.3)
select "Create Design for Xilinx Reference Boards"
change component name to "ddr_ctrl"
(Now quite some files are generated in the tmp directory)
There is now also a zip file in the tmp directory.
Now I click on the "Finish" button and get a message box with
"An Error Occured during Customisation"
What does this messsage want to tell me?
Thanks in advance for any info
03-13-2009 10:21 AM
As long as you have the zip file, then you have the board files you need which are in the zip file. The Coregen error may be a spurious error that can be ignored. Is your zip file valid? If so, I wouldn't worry about this Coregen error.
03-13-2009 10:57 AM
Thanks for your answer.
Yes, I have the zip film but is this all?
I expected, that there should be an easy way to insert the memory controller into an existing
project and a simple way to merge the ucf constraints.
How exactly is the intended, most painless flow to instantiate the SDRAM controller into an existing design
and being sure, that the constraints for the SDRAM controller er being merged.
My problem is mostly, that I am a first time user of Coregen and I don't really know what exactly to expect from the tool.
What I considered also strange is, that my error is not spirous, but 100% reproducable on two different computers.
If I generate for example a Fifo and not a memory controller, then CoreGn doesn't fail at the end
and the fifo becomes part of my coregen project.
A memory controller never becomes part of a coregen project, because coregen fails before.
03-13-2009 11:08 AM
In MIG, you should use "create new design" instead of the board files option if you are designing a new board. The output of MIG will then include two directories, an example design which includes a synthesizable test bench, and a user design which is the bare memory controller and physical layer. You would want to connect this user design to your overall design. The example design can be useful to simulate and to bring up your board. Both outputs from MIG include a UCF which you can incorporate in your larger design.
The board files option of MIG is for specific boards and will not necessarily be useful with a new design.
03-13-2009 11:51 AM
Well I didn't express myself very well.
I have an existing design (for me design = verilog code) for the Spartan 3AN starter kit with a few blocks, but without an SDRAM controller.
Therefore I wanted to choose im MIG the Spartan 3AN starter kit, such, that all the pin positions / timing constraints are correct.
It seems, that all, that MIG is doing when specifying a board is copying a pre-existing zip file into the tmp directory
The file could have been already found under
If MIG is just doing a mkdir, then a copy and then a crash, then I fully agree, that MIG is not really useful for this use case.
So I guess, that my 'design flow' seems to be this:
- copy the zip file manualy (or let MG copy it)
- unpack the zip file manually
- separate test bench files from the ddr controllerand copy them to my preexisting design
- locate the ucf file and manually merge the constraints
- do whatever else is needed to make the design run.
I think this will keep me busy for some time.
thanks again and bye
03-13-2009 12:28 PM