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Observer
Observer
2,634 Views
Registered: ‎03-08-2018

referenced RTL module and synthesis

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Hi all,

 

I am using Vivado 2017.1.

I have a design targeting for Ultra-Sclae device.

I use IP integrator based design and use "non-project mode" flow.

 

There is a verilog module referenced in Block design(say, xxx). During synthesis, all IPs in block design synthesized. But referenced RTL ended up with error.

 

This is the critical warning "Module references are not supported in manual compile order mode and will be ignored".

This is the error module 'xxx' not found.

 

I used set_property source_mgmt_mode All [current_project] in the synthesis script ( this information I got from forum).

Also I had added the RTL module to the project with read_verilog command.

 

Any help will be greatly appreciated.

 

Regards

SC

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Observer
Observer
2,501 Views
Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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@howardp,

 

Thank you very much for your help.

I checked my script again. But I could not find any reason for the reported problem.

 

But I got a solution.

As you mentioned in your first reply, my flow is a kind of project+non-project flow. Actually it was my misunderstanding that a vivado project must be created for implementing block design even if the flow is script based.

I removed the portion of creating the project from the script and avoided synthesizing OOC IPs in the loop. Now the flow is exactly like non-project mode and synthesis completed successfully.

 

I thank you for giving the hint to solve the problem.

 

Regards

SC

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Moderator
Moderator
2,620 Views
Registered: ‎09-15-2016

Re: referenced RTL module and synthesis

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Hi @soccerchamp

 

Can you check this in latest tool version 2018.1?

What happen when you use  set_property source_mgmt_mode All [current_project] in the synthesis script ?

Can you share the non-project mode tcl file?

To create a script with IPI design you can open the IPI in the GUI and do write_bd_tcl command. Now you can use these commands in the non-project tcl.

 

Also try creating a user IP instead of rtl referenced module and see if you face any issue.

Regards
Rohit
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Observer
Observer
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Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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@thakurr

 

Thanks for the reply.

 

<<Can you check this in latest tool version 2018.1?>>

I can try this option later only as there are many dependencies to change tool version now.

 

<<Can you share the non-project mode tcl file?>>

Attached. (I have changed the original project names and some logic). As you told, previously I had created a block design in GUI, write_bd_tcl to a TCL file and used that TCL file in this flow (wrapper_bd.tcl in my example script).

 

<<Also try creating a user IP instead of rtl referenced module and see if you face any issue.>>

When I package the RTL to IP, it works well. But I want to use referenced RTL method here if possible.

 

 

 

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Observer
Observer
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Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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@thakurr,

 

Did you get a chance to go through my script? Do you have any suggestion? (other than using vivado 2018 and packaging RTL to IP)

 

Regards

SC

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Moderator
Moderator
2,459 Views
Registered: ‎09-15-2016

Re: referenced RTL module and synthesis

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Hi @soccerchamp

 

Yes, I went through your script and script looks fine to me. Can you share the Vivado.log file ? I want to check at which step of the tcl, this error occurs.

Regards
Rohit
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Xilinx Employee
Xilinx Employee
2,451 Views
Registered: ‎07-22-2008

Re: referenced RTL module and synthesis

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@Anonymous,

 

Did you add the Verilog file to the project?

Module reference in a BD only works for files that have been added to the project (See pg 194 of UG994 - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug994-vivado-ip-subsystems.pdf#nameddest=xReferencingAModule). 

 

FYI: Your script appears to be part project (e.g. create_project does not use -in_memory) and part non-project (synth_design command used.  This is OK in some cases as there is a project in both cases (it is just not written to disk in the non-project / in-memory case).  However, it is best to stick with one flow if possible.

 

 

 

 

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Observer
Observer
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Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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Hello @howardp,

 

Thanks for your reply.

Yes I did add the file to project using read_verilog command. However I removed that portion from the sample script as it contained some project related names(I have marked the place using comment). Its only reading a file list, based on type of file, I used appropriate read command.

 

I just want to know if it is a limitation of the particular vivado version.

 

Regards

SC

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Observer
Observer
2,433 Views
Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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@thakurr,

Thanks for your efforts for helping me.

 

Sorry I am not able to share the log file in forum due to its confidential nature.

 

The error happened during the synthesis of blocks inside IP integrator. There is a loop in the script to synthesis each core. I had instantiated the referenced RTL 3 times in BD. Synthesis of all 3 blocks failed with below message.

 

critical warning:  "Module references are not supported in manual compile order mode and will be ignored".

Error: module 'xxx' not found.

 

As I mentioned in my first message, I had added the file to project. Also set the option set_property source_mgmt_mode All [current_project]

 

Regards

SC

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Xilinx Employee
Xilinx Employee
2,406 Views
Registered: ‎07-22-2008

Re: referenced RTL module and synthesis

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I ran a test project in Vivado 2017.1 using your basic script and it worked so It can be done.  

Can you try running the "set_property source_mgmt_mode All [current_project]" command and also run "update_compile_order -fileset sources_1" right before sourcing the BD tcl script?

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Observer
Observer
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Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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Hi @howardp,

 

Thanks for your support. Really appreciate it.

 

I tried this option. But did not work.

Could you mind sharing your script if there is no confidentiality issues? Just want to compare what I am missing.

 

Regards

SC

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Xilinx Employee
Xilinx Employee
1,812 Views
Registered: ‎07-22-2008

Re: referenced RTL module and synthesis

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Here are the files I used.  

build_proj.tcl is made from your script but I took out things that were not relevant to the test and changed it to reference my HDL files and build_bd3.tcl

build_bd3.tcl is created using write_bd_tcl.  I edited it to remove the SW version check so I could run it in both Vivado 2018.1 and 2017.1.  This is OK since there are no IP blocks in the BD, just a module reference and port connections.

debouncer.v, meta_harden, and clogb2.vh are all files from the wave_gen example design.

 

I was able to reproduce the error you got by explicitly setting the source management mode to "None" but not it I did nothing or set the mode to "All".

Removing files so they were not found or putting syntax errors in the HDL files caused different errors.

There is code in the software that will change the source management mode to None if the parser crashes during a parse.  From what you've explained, it does not seem like this is happening.

It may be worth checking the source_mgmt_mode (get_property source_mgmt_mode [current_project]) at various points to see if it is getting set to none some how.  If you are setting it to "All" right before sourcing the build BD script, maybe there is something inside that script that is causing it to revert to "None"

 

Observer
Observer
2,502 Views
Registered: ‎03-08-2018

Re: referenced RTL module and synthesis

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@howardp,

 

Thank you very much for your help.

I checked my script again. But I could not find any reason for the reported problem.

 

But I got a solution.

As you mentioned in your first reply, my flow is a kind of project+non-project flow. Actually it was my misunderstanding that a vivado project must be created for implementing block design even if the flow is script based.

I removed the portion of creating the project from the script and avoided synthesizing OOC IPs in the loop. Now the flow is exactly like non-project mode and synthesis completed successfully.

 

I thank you for giving the hint to solve the problem.

 

Regards

SC

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