01-09-2009 11:35 AM
I have software from MESA electronics to run a M5i20 board I/O board with Xilinx Spartan2 chip. The project file are in old NPL format and ISE successfully updates the project. However upon synthesis, a file sinetab.vhd is missing and ISE asks to regenerate this from sinetab.xco. Doing so results in a message stating that a coefficient file sine.coe is not found. Moving on ISE wants to regenerate fifomem.vhd and fifomem32.vhd. The former fails to rebuild for reasons that are not clear and the latter appear to rebuild successfully. The latter VHD file starts out with the statement "This file is owned and controlled by Xilinx ....", which implies that MESA has little to do with this core generation issue.
The ISE output is
Started : "Regenerate Core".
WARNING:sim:89 - A core named <sinetab> already exists in the output directory. Output products for this core may be overwritten.
ERROR:coreutil - File \\freeby\share\ISEPROJ\5i20\HOSTMOT\sine.coe not found.
ERROR:coreutil - Failure to set parameters on core: Invalid Coe File Name
ERROR:coreutil - Failure to generate output products
ERROR:coreutil:424 - An error occurred while running Java. Please examine the console or coregen log file for a specific IP related error.
For more information please search the Xilinx Answers Database for this error: http://www.xilinx.com/supportFinished Generating.
ERROR:sim:57 - Error found during generation
Started : "Regenerate Core".
WARNING:sim:89 - A core named <fifomem32> already exists in the output directory. Output products for this core may be overwritten.
Generating Implementation files.
Generating ISE symbol file...
Successfully generated fifomem32.
ERROR: Unable to find top-level VHDL source file fifomem.vhd
My questions are:
Who should I ask about this issue? Does MESA supply the sine.coe file or does Xilinx? (I sent a similar question to the folks at MESA too)
Is this just a trigonometric look-up table?
Where do I find the core fifomem32 in the output directory? Or can I?
Any ideas why fifomem.vhd is not generated?
And out of curiosity, why all the emphasis on "IP" in core generation? Clearly implementing a sine lookup table or a fifo buffer would not be intellectual property?
Many thanks for your help. Looking forward to your reply.
01-09-2009 12:25 PM
1) The .coe (coefficient file) specifies the initialization contents of the memory.
It appear that the .xco file is calling out a specific path for this file (e.g.\\freeby\share\ISEPROJ\5i20\HOSTMOT\sine.coe). I don't believe that the newer version of the sine look-up table core use a coe file. It is possible that you were provided this file from MESA and just need to update the .xco file to point to the correct file
http://www.xilinx.com/support/answers/15422.htm (10.1 CORE Generator - Can I edit the COE text field or directory location in the CORE Generator GUI?)
2) There may be some descrepancy between the core names (fifomem32 versus fifomem) here. It wouldn't hurt to check the xco file (e.g. open in a text editor) to see how this core was configured.
3) IP (intellectual property) is a generic term for copyright, patent, and/or trademark protection. It is also used commonly as a term to describe logic functions (e.g. cores) that have been developed for customer usage (either with or without additional license fees, depending on the specific core). The output of CoreGen includes source code and other files that may be protected by copyright (as evidenced by their headers). Some cores may also be covered by US and/or foreign patents, but I would guess this is a much smaller percentage.
[speaking for myself - not an official Xilinx position]
01-09-2009 03:16 PM
The path to sine.coe was probably specific to the folks at MESA but I could not find a similar file in any of the code downloaded from thier site. I think you are right that the new trig functions do not require look-up tables (at least not explicitly). I note that I still have on my bookshelf trig function tables from precalculator days.
The only significant difference between the fifomem and fifomem32 was the data width (i.e. 16 vs. 32) and the items specified in the project option. I will fool around with the options and see what happens. The folks from MESA are very helpful and may have some additional clues.
Thanks much for your quick response.
P.S. Some how I missed where to put an alias in my personal profile.
02-09-2010 05:05 PM
I kept running into this exact problem and was driving me nuts.
On the two occations when I ran into this problem that I could remember, I found that:
1) if you let your evaluation license expire, then the only thing coregen would do is give you a coreutil:424 error
and tell you there's a problem with java, when in fact java is behaving properly. if you just run 'xst' at the commandline all by itself, with no arguments, it would say your license has expired if this is your problem.
2) if you have a long windows path to your working directory (260 characters or so, I believe) then it'll also give you
this same error message. you can try moving your working directory to somewhere closer to 'root' and see if it helps.
Based on trying to track down the reason why I have this problem I believe the coreutil:424 is just a generic error message to indicate that some java code couldn't run properly, but there could many different reasons why java couldn't run.
Really wish Xilinx could fix these error messages to be more meaningful.