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Adventurer
Adventurer
8,173 Views
Registered: ‎02-11-2014

`timescale create any clocking issue during FPGA implemenation

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Hi,

Can we include `timescale in our implemeation code? or do we need to comment it during synthesis and implemation?? 

 

thanks

kathy

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Scholar
Scholar
14,791 Views
Registered: ‎11-21-2013

Kathy,

 

`timescale is not a synthesis directive, and therefore you can have it in your RTL.

 

BR

Vlad

Vladislav Muravin

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Scholar
Scholar
14,792 Views
Registered: ‎11-21-2013

Kathy,

 

`timescale is not a synthesis directive, and therefore you can have it in your RTL.

 

BR

Vlad

Vladislav Muravin

View solution in original post

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Teacher
Teacher
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Registered: ‎03-31-2012
`timescale and any time delays in RTL are ignored by synthesis so it's OK to leave them in.
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