unhide clock and reset in block diagram

[rutabagazuma]

The block diagram tool in vivado 2018.3 is configured to hide clock and reset connections in the design.   I believe there is a tcl command that can be used to show explicit nets between all drivers and receivers in the design, or at least on a net by net basis.  Examples shown in the attachment...

1) clocks with no explicit endpoint

2) clock and reset ports missing (removed) from sub systems when attached to other sources

3) clock sources with no explicit receivers.

I want my block diagram to not hide any connections.   

[rshekhaw]

HI @rutabagazuma ,

Please check this posts, might be helpful:

https://forums.xilinx.com/t5/Design-Entry/hidden-nets/td-p/650433

https://forums.xilinx.com/t5/Design-Entry/Diagram-Interface-goes-hidden-after-connection-how-to-disable/td-p/691589

Thanks,

Raj

[rutabagazuma]

The post on hidden nets offers control of net visibility.   It appears as though the control for this has changed between 2015 and 2018.3 versions.   It is not clear how to do this in 2018.3

[rutabagazuma · Accepted solution]

In vivado 2018.3 the settings for visiblity are accessed through the block diagram specific settings icon '*' on the top right of the block diagram window.

[luker]

in 2018.3 there is a setting in the IPI window that allows you to selectively display or hide the nets

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf#page=12