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Participant rutabagazuma
Participant
316 Views
Registered: ‎04-02-2019

unhide clock and reset in block diagram

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The block diagram tool in vivado 2018.3 is configured to hide clock and reset connections in the design.   I believe there is a tcl command that can be used to show explicit nets between all drivers and receivers in the design, or at least on a net by net basis.  Examples shown in the attachment...

1) clocks with no explicit endpoint

2) clock and reset ports missing (removed) from sub systems when attached to other sources

3) clock sources with no explicit receivers.

I want my block diagram to not hide any connections.   

Capture2.png
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Participant rutabagazuma
Participant
237 Views
Registered: ‎04-02-2019

Re: unhide clock and reset in block diagram

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In vivado 2018.3 the settings for visiblity are accessed through the block diagram specific settings icon '*' on the top right of the block diagram window.

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Xilinx Employee
Xilinx Employee
294 Views
Registered: ‎05-22-2018

Re: unhide clock and reset in block diagram

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Participant rutabagazuma
Participant
269 Views
Registered: ‎04-02-2019

Re: unhide clock and reset in block diagram

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The post on hidden nets offers control of net visibility.   It appears as though the control for this has changed between 2015 and 2018.3 versions.   It is not clear how to do this in 2018.3

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Participant rutabagazuma
Participant
238 Views
Registered: ‎04-02-2019

Re: unhide clock and reset in block diagram

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In vivado 2018.3 the settings for visiblity are accessed through the block diagram specific settings icon '*' on the top right of the block diagram window.

View solution in original post

Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎10-03-2018

Re: unhide clock and reset in block diagram

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in 2018.3 there is a setting in the IPI window that allows you to selectively display or hide the nets

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf#page=12

 

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