02-12-2019 02:06 AM
I'm using a vhdl package in an RTL module in a block design;
in the vhdl package there are some constant to use in the RTL module ports.
if the constant in the vhdl package is equal a number it is OK :
constant c_pixel_width : integer = 8 - this is OK
if the constant is equal a combination of other constants it doesnt recognize it in the RTL module:
constant c_pixel_width : integer := 8;
constant c_number_of_pix_per_clk : integer := 4;
constant c_vid_width : integer := c_pixel_width * c_number_of_pix_per_clk;
the RTL module, when I'm trying to instantiat it in the block diagram, is not recognize the c_vid_width constant
can anybody HELP me?
02-12-2019 02:19 AM
Can you share a test case for the issue?
02-12-2019 04:07 AM
Im using the attached package
and thos are the messages:
02-14-2019 06:04 AM - edited 02-15-2019 04:08 PM
@yotam "I'm using a vhdl package in an RTL module in a block design; in the vhdl package there are some constant to use in the RTL module ports."
Xilinx's IP packager (and I believe also the module reference flow) appear to use an ad-hoc parser that doesn't actually understand VHDL, it just 'scrapes' the source code for the generics and ports, requiring simplistic self-contained expressions in order to work.
I posted a summary of similar problems I'd seen, and pointers to what little Xilinx documentation exists, on this old thread from 2017:
" As a result, any generic and port expressions must be explicit and entirely self contained, nor does the fun stop there:
" - constants and functions defined in a package are not allowed in generic and port expressions
" - simple stuff, like an ( others => '0' ) initial value for a std_logic_vector generic, doesn't work
" - real generics, supported in ISE XPS, are not supported by Vivado IPI
" - port types are limited to plain-old-Verilog equivalents- no user defined types, records, etc.
" - OOC is bottom-up only, meaning all IP parameters must be hard-coded at the lower levels of the hierarchy
" - packaging System Verilog or VHDL-2008 is verboten
If you're seeing simple constants-in-packages now work in the module reference flow, it appears they have improved things slightly since I last checked; but judging by your error messages, Xilinx's questionably designed port/generic parsing code still does not appear to allow legal VHDL expressions within such constant declarations.
EDIT: I have confirmed the behavior you describe in 2018.3; module references can use a package constant in a port expression, but ONLY if the constant is defined by assignment to an explicit value - any expressions, or even a simple reference to another package constant, don't work.
As an ugly workaround, you might be able rewrite the problematic port range expressions to locally repeat the package calculations using just 'simple' constants defined within the package, but IIRC these port range expressions are also quite limited by the Vivado IP port parser.