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Visitor
Visitor
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Registered: ‎02-04-2009

verilog files loading order

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Hi all,

 

I am trying to a synthesis a large IP into FPGA.

This IP has a lot of verilog files  (origenly form ASIC design) and some modules instantiation are done thru define declaration.

I can see that project navigator is unable to instantiates module which are perversely read.

Is there a way to control module instantiated or file compile, order so the instantiation will be done proper?

 

Thanks,

 

Nitzan

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Professor
Professor
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Registered: ‎08-14-2007

Re: verilog files loading order

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The standard method for global defines is to use an include file.

 

Your include file contains all of the `define that need to be global for the project.

 

Your other modules that rely on these definitions include this file with `include "filename"

 

If you only need one or two global defines, you can do it in the ISE "Synthesis Properties"

under the tab "Verilog Macros" where you can type your definitions, without the `define keyword

and they will be included in the command line when your Verilog modules are compiled.

 

It is generally not a good idea to rely on the order of compilation for global definitions.

-- Gabor

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Professor
Professor
8,312 Views
Registered: ‎08-14-2007

Re: verilog files loading order

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The standard method for global defines is to use an include file.

 

Your include file contains all of the `define that need to be global for the project.

 

Your other modules that rely on these definitions include this file with `include "filename"

 

If you only need one or two global defines, you can do it in the ISE "Synthesis Properties"

under the tab "Verilog Macros" where you can type your definitions, without the `define keyword

and they will be included in the command line when your Verilog modules are compiled.

 

It is generally not a good idea to rely on the order of compilation for global definitions.

-- Gabor

View solution in original post

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Visitor
Visitor
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Registered: ‎02-04-2009

Re: verilog files loading order

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Solved in ISE 10.1
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Historian
Historian
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Registered: ‎02-25-2008

Re: verilog files loading order

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nmpr wrote:

 

I am trying to a synthesis a large IP into FPGA.

This IP has a lot of verilog files  (origenly form ASIC design) and some modules instantiation are done thru define declaration.



Why did the IP vendor do that? It's completely unncessary. Using `include to `include a Verilog source file is like using #include "myfuncs.c" in a C program!

 

-a

----------------------------Yes, I do this for a living.
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