cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
3,043 Views
Registered: ‎09-20-2016

vivado 2014 - using bare HDL file without IP packaging

Jump to solution

I'm using vivado 2014 and want add a hdl file into the design diagram.

 

Is there anyway to use it without packing this bare file into an IP?

 

Thanks.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
5,511 Views
Registered: ‎08-01-2008
Yes there is no other option. You need to package vhdl file

Package your design using Vivado IP packager. After this add the IP repository to your block design project IP catalog. After this you can see your custom IP in "ADD IP" of block design.
Check these for more details

chapter-8 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf

lab-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug939-vivado-designing-with-ip-tutorial.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos
4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
3,034 Views
Registered: ‎08-01-2008
yes you can add directly with add file option .
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Visitor
Visitor
3,027 Views
Registered: ‎09-20-2016

How can I do that ? From the flow navigator or right click in the block design window?

 

I didn't saw an option called "add file". 

 

There's an "add sources" option in the project manager menu, but it can just add diagram design files..

The right click in the block design windows just have something like "add IP".

 

Thanks again.

0 Kudos
Highlighted
Visitor
Visitor
3,024 Views
Registered: ‎09-20-2016

I mean, I want make the HDL file show up as a block in the diagram design windows. Don't know how to operate it.

 

I feel that it's too stupid to package every single HDL file into an IP in some light applications. 

Highlighted
Xilinx Employee
Xilinx Employee
5,512 Views
Registered: ‎08-01-2008
Yes there is no other option. You need to package vhdl file

Package your design using Vivado IP packager. After this add the IP repository to your block design project IP catalog. After this you can see your custom IP in "ADD IP" of block design.
Check these for more details

chapter-8 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf

lab-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug939-vivado-designing-with-ip-tutorial.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

0 Kudos