vivado 2017.2 ignore unused pin

[s002wjhw]

is there way to tell vivado not to give error for unused pins?  or tell it to ignore it.

[hpoetzl]

Hey @s002wjhw,

I don't remember Vivado ever complaining about unused pins.

Maybe give an example for the Warning or Error you are seeing?

Best,

Herbert

[umamahe]

I believe Vivado do not to give error for unused pins. Please refer below answer records for more details

https://www.xilinx.com/support/answers/62560.html

https://www.xilinx.com/support/answers/68114.html

[s002wjhw]

well I receive these errors, and looking at XDC constraint, these pins is not assigned anywhere.

[s002wjhw]

also I run this in 2014.4, and it compile fine, I didn't upgrade all the IP when running in 2017.2 ( MIG core)

[hpoetzl]

@s002wjhw

The image shows 32 unplaced terminals.

Vivado is trying to place the listed output ports (AMX_*, FMC*) on pins which conform to the specified LVCMOS18 I/O standard and group, but at this point, there are none left.

Hope this helps,

Herbert

[s002wjhw]

yes but this doesn't explain why the same project run flawless on 2014.4 but not on 2017.2 the only thing I did was upgrade the ip, all constraint are same. these pins are MGT pairs.

[hpoetzl]

@s002wjhw  ... the only thing I did was upgrade the ip ...

Well, the IP is a huge part with many, many files, some of them will affect the synthesis (mostly the HDL), some of them will contain constraints and that is where I would start to look.

I.e. compare the IP related constraints before the upgrade with the ones from after the upgrade.

Hope this helps,

Herbert