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Adventurer
Adventurer
4,414 Views
Registered: ‎06-27-2009

what's the process for programming the device with ipcore-based projects?

i have a new project in Project Navigator. the only source i added was an ipcore (a 7-bit adder). The "ip" was succesfully generated but i don't know what i have to do to add constraints (and assign i/o pins with plan ahead), synthetize it, generate bitstream and program device (with impact).  Which is the process with that kind of project?

 

thank you very much!!

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3 Replies
Adventurer
Adventurer
4,397 Views
Registered: ‎06-27-2009

Re: what's the process for programming the device with ipcore-based projects?

please ...   i'm only trying to learn how to use ipcores.  ;)

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Historian
Historian
4,395 Views
Registered: ‎02-25-2008

Re: what's the process for programming the device with ipcore-based projects?


black_flowers wrote:

i have a new project in Project Navigator. the only source i added was an ipcore (a 7-bit adder). The "ip" was succesfully generated but i don't know what i have to do to add constraints (and assign i/o pins with plan ahead), synthetize it, generate bitstream and program device (with impact).  Which is the process with that kind of project?

 

thank you very much!!


IP cores are used as part of a larger design.

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
4,252 Views
Registered: ‎12-17-2007

Re: what's the process for programming the device with ipcore-based projects?

black_flowers,

 

Here is a fairly quick summary of the intended design flow for IP cores.

 

1) you create or purchase an IP core.  the instruction below assume that the core is strictly distributed as a netlist, not code.

 

2) the IP core will include what is called an instantiation template.  This is either VHDL/Verilog code or a schematic entry symbol that represents the core at a high level.  You include this template/schematic symbol in your design.

 

3) When you synthesize the design, the section of the design for the IP core is recognized as being "empty" and is blackboxed during synthesis.

 

4) During NGDBuild/Translate, the netlist for your cores are read in and then they are "stiched" into place inside the over netlist coming out of the synthesis tool.  These are then combined with your constraints to produce a monolithic design netlist -- the NGD

 

5) The NGD is then passed to MAP which produces a post-MAP NCD which is sent to PAR

 

6) PAR takes the post-MAP NCD and creates a post-PAR NCD which is then used for timing analysis and generation of the final BitStream.

 

For the constraints file (UCF), you can either write this by hand or use a tool such as Constraints Editor or PlanAhead.  If you need to constrain blocks and/or nets inside of the core, then you'll either need to know the internal structure of the core (so that you can specify correctly fully qualified constraints to the block/net hierarchical name) or you can use wildcards in your constraints for large-scale constraint matching.

 

 

 

 

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